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MIR Parser: Implicit register verifier should accept unexpected implicit 

subregister operands.

llvm-svn: 245315
This commit is contained in:
Alex Lorenz 2015-08-18 17:17:13 +00:00
parent 1846ea3c71
commit eb7c9be43c
2 changed files with 43 additions and 0 deletions
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13
llvm/lib/CodeGen/MIRParser/MIParser.cpp
View File

@ -695,6 +695,19 @@ bool MIParser::verifyImplicitOperands(
if (ImplicitOperand.isIdenticalTo(Operand))
continue;
if (Operand.isReg() && Operand.isImplicit()) {
// Check if this implicit register is a subregister of an explicit
// register operand.
bool IsImplicitSubRegister = false;
for (size_t K = 0, E = Operands.size(); K < E; ++K) {
const auto &Op = Operands[K].Operand;
if (Op.isReg() && !Op.isImplicit() &&
TRI->isSubRegister(Op.getReg(), Operand.getReg())) {
IsImplicitSubRegister = true;
break;
}
}
if (IsImplicitSubRegister)
continue;
return error(Operands[J].Begin,
Twine("expected an implicit register operand '") +
printImplicitRegisterFlag(ImplicitOperand) + " %" +

30
llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir
View File

@ -16,6 +16,16 @@
ret i32 %a
}
define i1 @implicit_subregister1() {
entry:
ret i1 false
}
define i16 @implicit_subregister2() {
entry:
ret i16 0
}
...
---
name: foo
@ -36,3 +46,23 @@ body: |
%eax = COPY %edi
RETQ %eax
...
---
name: implicit_subregister1
body: |
bb.0.entry:
; Verify that the implicit register verifier won't report an error on implicit
; subregisters.
; CHECK-LABEL: name: implicit_subregister1
; CHECK: dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
dead %eax = XOR32rr undef %eax, undef %eax, implicit-def dead %eflags, implicit-def %al
RETQ killed %al
...
---
name: implicit_subregister2
body: |
bb.0.entry:
; CHECK-LABEL: name: implicit_subregister2
; CHECK: dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w
dead %r15 = XOR64rr undef %r15, undef %r15, implicit-def dead %eflags, implicit-def %r15w
RETQ killed %r15w
...