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ARM VST1 single lane assembly parsing. 

llvm-svn: 145718
This commit is contained in:
Jim Grosbach 2011-12-02 22:34:51 +00:00
parent 430f917fbe
commit eb53822f5a
2 changed files with 179 additions and 4 deletions
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29
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -5620,3 +5620,32 @@ defm VLD1LNdWB_register_Asm :
NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
// VST1 single-lane pseudo-instructions. These need special handling for
// the lane index that an InstAlias can't handle, so we use these instead.
defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
defm VST1LNdWB_register_Asm :
NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
defm VST1LNdWB_register_Asm :
NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;
defm VST1LNdWB_register_Asm :
NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
(ins VecListOneDByteIndexed:$list, addrmode6:$addr,
rGPR:$Rm, pred:$p)>;

154
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -4751,7 +4751,61 @@ validateInstruction(MCInst &Inst,
return false;
}
static unsigned getRealVLDNOpcode(unsigned Opc) {
static unsigned getRealVSTLNOpcode(unsigned Opc) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
case ARM::VST1LNdWB_fixed_Asm_8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_P8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_I8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_S8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_U8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_fixed_Asm_16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_fixed_Asm_P16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_fixed_Asm_I16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_fixed_Asm_S16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_fixed_Asm_U16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_fixed_Asm_32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_fixed_Asm_F: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_fixed_Asm_F32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_fixed_Asm_I32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_fixed_Asm_S32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_fixed_Asm_U32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_register_Asm_P8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_register_Asm_I8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_register_Asm_S8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_register_Asm_U8: return ARM::VST1LNd8_UPD;
case ARM::VST1LNdWB_register_Asm_16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_register_Asm_P16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_register_Asm_I16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_register_Asm_S16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_register_Asm_U16: return ARM::VST1LNd16_UPD;
case ARM::VST1LNdWB_register_Asm_32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_F: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_F32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_I32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_S32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdWB_register_Asm_U32: return ARM::VST1LNd32_UPD;
case ARM::VST1LNdAsm_8: return ARM::VST1LNd8;
case ARM::VST1LNdAsm_P8: return ARM::VST1LNd8;
case ARM::VST1LNdAsm_I8: return ARM::VST1LNd8;
case ARM::VST1LNdAsm_S8: return ARM::VST1LNd8;
case ARM::VST1LNdAsm_U8: return ARM::VST1LNd8;
case ARM::VST1LNdAsm_16: return ARM::VST1LNd16;
case ARM::VST1LNdAsm_P16: return ARM::VST1LNd16;
case ARM::VST1LNdAsm_I16: return ARM::VST1LNd16;
case ARM::VST1LNdAsm_S16: return ARM::VST1LNd16;
case ARM::VST1LNdAsm_U16: return ARM::VST1LNd16;
case ARM::VST1LNdAsm_32: return ARM::VST1LNd32;
case ARM::VST1LNdAsm_F: return ARM::VST1LNd32;
case ARM::VST1LNdAsm_F32: return ARM::VST1LNd32;
case ARM::VST1LNdAsm_I32: return ARM::VST1LNd32;
case ARM::VST1LNdAsm_S32: return ARM::VST1LNd32;
case ARM::VST1LNdAsm_U32: return ARM::VST1LNd32;
}
}
static unsigned getRealVLDLNOpcode(unsigned Opc) {
switch(Opc) {
default: assert(0 && "unexpected opcode!");
case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
@ -4809,6 +4863,98 @@ bool ARMAsmParser::
processInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
switch (Inst.getOpcode()) {
// Handle NEON VST1 complex aliases.
case ARM::VST1LNdWB_register_Asm_8:
case ARM::VST1LNdWB_register_Asm_P8:
case ARM::VST1LNdWB_register_Asm_I8:
case ARM::VST1LNdWB_register_Asm_S8:
case ARM::VST1LNdWB_register_Asm_U8:
case ARM::VST1LNdWB_register_Asm_16:
case ARM::VST1LNdWB_register_Asm_P16:
case ARM::VST1LNdWB_register_Asm_I16:
case ARM::VST1LNdWB_register_Asm_S16:
case ARM::VST1LNdWB_register_Asm_U16:
case ARM::VST1LNdWB_register_Asm_32:
case ARM::VST1LNdWB_register_Asm_F:
case ARM::VST1LNdWB_register_Asm_F32:
case ARM::VST1LNdWB_register_Asm_I32:
case ARM::VST1LNdWB_register_Asm_S32:
case ARM::VST1LNdWB_register_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(4)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(5)); // CondCode
TmpInst.addOperand(Inst.getOperand(6));
Inst = TmpInst;
return true;
}
case ARM::VST1LNdWB_fixed_Asm_8:
case ARM::VST1LNdWB_fixed_Asm_P8:
case ARM::VST1LNdWB_fixed_Asm_I8:
case ARM::VST1LNdWB_fixed_Asm_S8:
case ARM::VST1LNdWB_fixed_Asm_U8:
case ARM::VST1LNdWB_fixed_Asm_16:
case ARM::VST1LNdWB_fixed_Asm_P16:
case ARM::VST1LNdWB_fixed_Asm_I16:
case ARM::VST1LNdWB_fixed_Asm_S16:
case ARM::VST1LNdWB_fixed_Asm_U16:
case ARM::VST1LNdWB_fixed_Asm_32:
case ARM::VST1LNdWB_fixed_Asm_F:
case ARM::VST1LNdWB_fixed_Asm_F32:
case ARM::VST1LNdWB_fixed_Asm_I32:
case ARM::VST1LNdWB_fixed_Asm_S32:
case ARM::VST1LNdWB_fixed_Asm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
Inst = TmpInst;
return true;
}
case ARM::VST1LNdAsm_8:
case ARM::VST1LNdAsm_P8:
case ARM::VST1LNdAsm_I8:
case ARM::VST1LNdAsm_S8:
case ARM::VST1LNdAsm_U8:
case ARM::VST1LNdAsm_16:
case ARM::VST1LNdAsm_P16:
case ARM::VST1LNdAsm_I16:
case ARM::VST1LNdAsm_S16:
case ARM::VST1LNdAsm_U16:
case ARM::VST1LNdAsm_32:
case ARM::VST1LNdAsm_F:
case ARM::VST1LNdAsm_F32:
case ARM::VST1LNdAsm_I32:
case ARM::VST1LNdAsm_S32:
case ARM::VST1LNdAsm_U32: {
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(1)); // lane
TmpInst.addOperand(Inst.getOperand(4)); // CondCode
TmpInst.addOperand(Inst.getOperand(5));
Inst = TmpInst;
return true;
}
// Handle NEON VLD1 complex aliases.
case ARM::VLD1LNdWB_register_Asm_8:
case ARM::VLD1LNdWB_register_Asm_P8:
@ -4829,7 +4975,7 @@ processInstruction(MCInst &Inst,
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
@ -4861,7 +5007,7 @@ processInstruction(MCInst &Inst,
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(2)); // Rn
@ -4893,7 +5039,7 @@ processInstruction(MCInst &Inst,
MCInst TmpInst;
// Shuffle the operands around so the lane index operand is in the
// right place.
TmpInst.setOpcode(getRealVLDNOpcode(Inst.getOpcode()));
TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
TmpInst.addOperand(Inst.getOperand(0)); // Vd
TmpInst.addOperand(Inst.getOperand(2)); // Rn
TmpInst.addOperand(Inst.getOperand(3)); // alignment