R600/SI: Remove M0 from DS assembly strings
This matches the assembly syntax for the proprietary compiler. llvm-svn: 230645
This commit is contained in:
Tom Stellard
parent
6e09bca0ef
commit
eb05c610b4
|
|
@ -1523,7 +1523,7 @@ multiclass DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass>
|
|||
asm,
|
||||
(outs regClass:$vdst),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, ds_offset:$offset, M0Reg:$m0),
|
||||
asm#" $vdst, $addr"#"$offset"#" [M0]",
|
||||
asm#" $vdst, $addr"#"$offset",
|
||||
[]>;
|
||||
|
||||
multiclass DS_Load2_m <bits<8> op, string opName, dag outs, dag ins, string asm,
|
||||
|
|
@ -1545,7 +1545,7 @@ multiclass DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass>
|
|||
(outs regClass:$vdst),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,
|
||||
M0Reg:$m0),
|
||||
asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",
|
||||
asm#" $vdst, $addr"#"$offset0"#"$offset1",
|
||||
[]>;
|
||||
|
||||
multiclass DS_1A_Store_m <bits<8> op, string opName, dag outs, dag ins,
|
||||
|
|
@ -1566,7 +1566,7 @@ multiclass DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass>
|
|||
asm,
|
||||
(outs),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),
|
||||
asm#" $addr, $data0"#"$offset"#" [M0]",
|
||||
asm#" $addr, $data0"#"$offset",
|
||||
[]>;
|
||||
|
||||
multiclass DS_Store_m <bits<8> op, string opName, dag outs, dag ins,
|
||||
|
|
@ -1588,7 +1588,7 @@ multiclass DS_Store2_Helper <bits<8> op, string asm, RegisterClass regClass>
|
|||
(outs),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, regClass:$data0, regClass:$data1,
|
||||
ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),
|
||||
asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",
|
||||
asm#" $addr, $data0, $data1"#"$offset0"#"$offset1",
|
||||
[]>;
|
||||
|
||||
// 1 address, 1 data.
|
||||
|
|
@ -1612,7 +1612,7 @@ multiclass DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc,
|
|||
op, asm,
|
||||
(outs rc:$vdst),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
|
||||
asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", [], noRetOp>;
|
||||
asm#" $vdst, $addr, $data0"#"$offset", [], noRetOp>;
|
||||
|
||||
// 1 address, 2 data.
|
||||
multiclass DS_1A2D_RET_m <bits<8> op, string opName, dag outs, dag ins,
|
||||
|
|
@ -1633,7 +1633,7 @@ multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc,
|
|||
op, asm,
|
||||
(outs rc:$vdst),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
|
||||
asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",
|
||||
asm#" $vdst, $addr, $data0, $data1"#"$offset",
|
||||
[], noRetOp>;
|
||||
|
||||
// 1 address, 2 data.
|
||||
|
|
@ -1655,7 +1655,7 @@ multiclass DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc,
|
|||
op, asm,
|
||||
(outs),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),
|
||||
asm#" $addr, $data0, $data1"#"$offset"#" [M0]",
|
||||
asm#" $addr, $data0, $data1"#"$offset",
|
||||
[], noRetOp>;
|
||||
|
||||
// 1 address, 1 data.
|
||||
|
|
@ -1677,7 +1677,7 @@ multiclass DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc,
|
|||
op, asm,
|
||||
(outs),
|
||||
(ins i1imm:$gds, VGPR_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),
|
||||
asm#" $addr, $data0"#"$offset"#" [M0]",
|
||||
asm#" $addr, $data0"#"$offset",
|
||||
[], noRetOp>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
|
|||
|
|
@ -131,7 +131,7 @@ define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %v
|
|||
; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store:
|
||||
; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
|
||||
; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
||||
; SI: ds_write_b32 [[VPTR]], v{{[0-9]+}} [M0]{{$}}
|
||||
; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
|
||||
define void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
|
||||
%gep = getelementptr i32 addrspace(3)* %out, i32 16385
|
||||
store i32 %val, i32 addrspace(3)* %gep, align 4
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
|
||||
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
|
||||
; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
|
||||
; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0]
|
||||
; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap) nounwind {
|
||||
%gep = getelementptr i32 addrspace(3)* %ptr, i32 4
|
||||
|
|
@ -30,7 +30,7 @@ define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrs
|
|||
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
|
||||
; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
|
||||
; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
|
||||
; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
|
||||
; GCN: ds_cmpst_rtn_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
|
||||
; GCN: buffer_store_dwordx2 [[RESULT]],
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr, i64 %swap) nounwind {
|
||||
|
|
@ -43,7 +43,7 @@ define void @lds_atomic_cmpxchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrs
|
|||
|
||||
; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_bad_si_offset
|
||||
; SI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; CIVI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0]
|
||||
; CIVI: ds_cmpst_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %swap, i32 %a, i32 %b) nounwind {
|
||||
%sub = sub i32 %a, %b
|
||||
|
|
@ -63,7 +63,7 @@ define void @lds_atomic_cmpxchg_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i3
|
|||
; GCN-DAG: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7
|
||||
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
|
||||
; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]]
|
||||
; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 [M0]
|
||||
; GCN: ds_cmpst_b32 [[VPTR]], [[VCMP]], [[VSWAP]] offset:16
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %swap) nounwind {
|
||||
%gep = getelementptr i32 addrspace(3)* %ptr, i32 4
|
||||
|
|
@ -82,7 +82,7 @@ define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %sw
|
|||
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
|
||||
; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]]
|
||||
; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]]
|
||||
; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32 [M0]
|
||||
; GCN: ds_cmpst_b64 [[VPTR]], v{{\[}}[[LOVCMP]]:[[HIVCMP]]{{\]}}, v{{\[}}[[LOSWAPV]]:[[HISWAPV]]{{\]}} offset:32
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_cmpxchg_noret_i64_offset(i64 addrspace(3)* %ptr, i64 %swap) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %ptr, i32 4
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
; SI-LABEL: @simple_write2_one_val_f32
|
||||
; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -25,7 +25,7 @@ define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1
|
|||
; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -84,7 +84,7 @@ define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float
|
|||
; SI: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:{{[0-9]+\]}}
|
||||
; SI: buffer_load_dwordx2 v{{\[[0-9]+}}:[[VAL1:[0-9]+]]{{\]}}
|
||||
; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -105,7 +105,7 @@ define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2
|
|||
; SI-LABEL: @simple_write2_two_val_subreg2_f32
|
||||
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -124,7 +124,7 @@ define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x floa
|
|||
; SI-LABEL: @simple_write2_two_val_subreg4_f32
|
||||
; SI-DAG: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -144,7 +144,7 @@ define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x floa
|
|||
; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -268,7 +268,7 @@ define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float add
|
|||
; SI-LABEL: @simple_write2_one_val_f64
|
||||
; SI: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]],
|
||||
; SI: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
|
||||
; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -285,8 +285,8 @@ define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace
|
|||
; SI-LABEL: @misaligned_simple_write2_one_val_f64
|
||||
; SI-DAG: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:1 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 [M0]
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:0 offset1:1
|
||||
; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15
|
||||
; SI: s_endpgm
|
||||
define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -304,7 +304,7 @@ define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, doubl
|
|||
; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 3, v{{[0-9]+}}
|
||||
; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8 [M0]
|
||||
; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:8
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
; SI-LABEL: @simple_write2st64_one_val_f32_0_1
|
||||
; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1 [M0]
|
||||
; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset0:0 offset1:1
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -25,7 +25,7 @@ define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float add
|
|||
; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 [M0]
|
||||
; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -46,7 +46,7 @@ define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float add
|
|||
; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
|
||||
; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255 [M0]
|
||||
; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:0 offset1:255
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -66,7 +66,7 @@ define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, fl
|
|||
; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
|
||||
; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
|
||||
; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]],
|
||||
; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 [M0]
|
||||
; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
|
||||
; SI: s_endpgm
|
||||
define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
|
||||
%x.i = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=BOTH %s
|
||||
|
||||
; BOTH-LABEL: {{^}}local_i32_load
|
||||
; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28 [M0]
|
||||
; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} offset:28
|
||||
; BOTH: buffer_store_dword [[REG]],
|
||||
define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i32 addrspace(3)* %in, i32 7
|
||||
|
|
@ -13,7 +13,7 @@ define void @local_i32_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounw
|
|||
}
|
||||
|
||||
; BOTH-LABEL: {{^}}local_i32_load_0_offset
|
||||
; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}} [M0]
|
||||
; BOTH: ds_read_b32 [[REG:v[0-9]+]], v{{[0-9]+}}
|
||||
; BOTH: buffer_store_dword [[REG]],
|
||||
define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) nounwind {
|
||||
%val = load i32 addrspace(3)* %in, align 4
|
||||
|
|
@ -23,7 +23,7 @@ define void @local_i32_load_0_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %
|
|||
|
||||
; BOTH-LABEL: {{^}}local_i8_load_i16_max_offset:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535 [M0]
|
||||
; BOTH: ds_read_u8 [[REG:v[0-9]+]], {{v[0-9]+}} offset:65535
|
||||
; BOTH: buffer_store_byte [[REG]],
|
||||
define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i8 addrspace(3)* %in, i32 65535
|
||||
|
|
@ -38,7 +38,7 @@ define void @local_i8_load_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
|
|||
; SI: s_or_b32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
|
||||
; CI: s_add_i32 [[ADDR:s[0-9]+]], s{{[0-9]+}}, 0x10000
|
||||
; BOTH: v_mov_b32_e32 [[VREGADDR:v[0-9]+]], [[ADDR]]
|
||||
; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]] [M0]
|
||||
; BOTH: ds_read_u8 [[REG:v[0-9]+]], [[VREGADDR]]
|
||||
; BOTH: buffer_store_byte [[REG]],
|
||||
define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i8 addrspace(3)* %in, i32 65536
|
||||
|
|
@ -49,7 +49,7 @@ define void @local_i8_load_over_i16_max_offset(i8 addrspace(1)* %out, i8 addrspa
|
|||
|
||||
; BOTH-LABEL: {{^}}local_i64_load:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0]
|
||||
; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
|
||||
; BOTH: buffer_store_dwordx2 [[REG]],
|
||||
define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %in, i32 7
|
||||
|
|
@ -59,7 +59,7 @@ define void @local_i64_load(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounw
|
|||
}
|
||||
|
||||
; BOTH-LABEL: {{^}}local_i64_load_0_offset
|
||||
; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0]
|
||||
; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
|
||||
; BOTH: buffer_store_dwordx2 [[REG]],
|
||||
define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %in) nounwind {
|
||||
%val = load i64 addrspace(3)* %in, align 8
|
||||
|
|
@ -69,7 +69,7 @@ define void @local_i64_load_0_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %
|
|||
|
||||
; BOTH-LABEL: {{^}}local_f64_load:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56 [M0]
|
||||
; BOTH: ds_read_b64 [[REG:v[[0-9]+:[0-9]+]]], v{{[0-9]+}} offset:56
|
||||
; BOTH: buffer_store_dwordx2 [[REG]],
|
||||
define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
|
||||
%gep = getelementptr double addrspace(3)* %in, i32 7
|
||||
|
|
@ -79,7 +79,7 @@ define void @local_f64_load(double addrspace(1)* %out, double addrspace(3)* %in)
|
|||
}
|
||||
|
||||
; BOTH-LABEL: {{^}}local_f64_load_0_offset
|
||||
; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} [M0]
|
||||
; BOTH: ds_read_b64 [[REG:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}
|
||||
; BOTH: buffer_store_dwordx2 [[REG]],
|
||||
define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace(3)* %in) nounwind {
|
||||
%val = load double addrspace(3)* %in, align 8
|
||||
|
|
@ -89,7 +89,7 @@ define void @local_f64_load_0_offset(double addrspace(1)* %out, double addrspace
|
|||
|
||||
; BOTH-LABEL: {{^}}local_i64_store:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0]
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
|
||||
define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %out, i32 7
|
||||
store i64 5678, i64 addrspace(3)* %gep, align 8
|
||||
|
|
@ -98,7 +98,7 @@ define void @local_i64_store(i64 addrspace(3)* %out) nounwind {
|
|||
|
||||
; BOTH-LABEL: {{^}}local_i64_store_0_offset:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
|
||||
define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
|
||||
store i64 1234, i64 addrspace(3)* %out, align 8
|
||||
ret void
|
||||
|
|
@ -106,7 +106,7 @@ define void @local_i64_store_0_offset(i64 addrspace(3)* %out) nounwind {
|
|||
|
||||
; BOTH-LABEL: {{^}}local_f64_store:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56 [M0]
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:56
|
||||
define void @local_f64_store(double addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr double addrspace(3)* %out, i32 7
|
||||
store double 16.0, double addrspace(3)* %gep, align 8
|
||||
|
|
@ -114,7 +114,7 @@ define void @local_f64_store(double addrspace(3)* %out) nounwind {
|
|||
}
|
||||
|
||||
; BOTH-LABEL: {{^}}local_f64_store_0_offset
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
|
||||
; BOTH: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
|
||||
define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
|
||||
store double 20.0, double addrspace(3)* %out, align 8
|
||||
ret void
|
||||
|
|
@ -122,8 +122,8 @@ define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind {
|
|||
|
||||
; BOTH-LABEL: {{^}}local_v2i64_store:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120
|
||||
; BOTH: s_endpgm
|
||||
define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr <2 x i64> addrspace(3)* %out, i32 7
|
||||
|
|
@ -133,8 +133,8 @@ define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind {
|
|||
|
||||
; BOTH-LABEL: {{^}}local_v2i64_store_0_offset:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
|
||||
; BOTH: s_endpgm
|
||||
define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
|
||||
store <2 x i64> <i64 1234, i64 1234>, <2 x i64> addrspace(3)* %out, align 16
|
||||
|
|
@ -143,10 +143,10 @@ define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind {
|
|||
|
||||
; BOTH-LABEL: {{^}}local_v4i64_store:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248
|
||||
; BOTH: s_endpgm
|
||||
define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
%gep = getelementptr <4 x i64> addrspace(3)* %out, i32 7
|
||||
|
|
@ -156,10 +156,10 @@ define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind {
|
|||
|
||||
; BOTH-LABEL: {{^}}local_v4i64_store_0_offset:
|
||||
; BOTH-NOT: ADD
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24 [M0]
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16
|
||||
; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24
|
||||
; BOTH: s_endpgm
|
||||
define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind {
|
||||
store <4 x i64> <i64 1234, i64 1234, i64 1234, i64 1234>, <4 x i64> addrspace(3)* %out, align 16
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
|
||||
; GCN: s_load_dword [[SPTR:s[0-9]+]],
|
||||
; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
||||
; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0]
|
||||
; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
|
||||
; GCN: buffer_store_dword [[RESULT]],
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_xchg_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
|
||||
|
|
@ -34,7 +34,7 @@ define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac
|
|||
; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
|
||||
; GCN: s_load_dword [[SPTR:s[0-9]+]],
|
||||
; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
||||
; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0]
|
||||
; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
|
||||
; GCN: buffer_store_dword [[RESULT]],
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_add_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
|
||||
|
|
@ -56,7 +56,7 @@ define void @lds_atomic_add_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
|
|||
|
||||
; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_bad_si_offset:
|
||||
; EG: LDS_ADD_RET *
|
||||
; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0]
|
||||
; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
|
||||
|
|
@ -71,7 +71,7 @@ define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 ad
|
|||
; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32:
|
||||
; EG: LDS_ADD_RET *
|
||||
; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
|
||||
; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0]
|
||||
; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]]
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
|
||||
%result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst
|
||||
|
|
@ -93,7 +93,7 @@ define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
|
|||
|
||||
; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_bad_si_offset:
|
||||
; EG: LDS_ADD_RET *
|
||||
; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} [M0]
|
||||
; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; CIVI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_inc_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
|
||||
|
|
@ -129,7 +129,7 @@ define void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace
|
|||
; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32:
|
||||
; EG: LDS_SUB_RET *
|
||||
; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
|
||||
; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] [M0]
|
||||
; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]]
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
|
||||
%result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst
|
||||
|
|
@ -308,7 +308,7 @@ define void @lds_atomic_umax_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac
|
|||
; GCN: s_load_dword [[SPTR:s[0-9]+]],
|
||||
; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
|
||||
; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
||||
; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] [M0]
|
||||
; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_xchg_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
||||
%result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst
|
||||
|
|
@ -329,7 +329,7 @@ define void @lds_atomic_xchg_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|||
; GCN: s_load_dword [[SPTR:s[0-9]+]],
|
||||
; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
|
||||
; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
||||
; GCN: ds_add_u32 [[VPTR]], [[DATA]] [M0]
|
||||
; GCN: ds_add_u32 [[VPTR]], [[DATA]]
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_add_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
||||
%result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst
|
||||
|
|
@ -346,8 +346,8 @@ define void @lds_atomic_add_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_bad_si_offset
|
||||
; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} [M0]
|
||||
; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 [M0]
|
||||
; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}}
|
||||
; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
|
||||
%sub = sub i32 %a, %b
|
||||
|
|
@ -359,7 +359,7 @@ define void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32
|
|||
|
||||
; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32:
|
||||
; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1
|
||||
; GCN: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] [M0]
|
||||
; GCN: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]]
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
||||
%result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p
|
|||
; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
|
||||
; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
|
||||
; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
|
||||
; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0]
|
||||
; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
|
||||
; GCN: buffer_store_dwordx2 [[RESULT]],
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind {
|
||||
|
|
@ -280,7 +280,7 @@ define void @lds_atomic_add_noret_i64(i64 addrspace(3)* %ptr) nounwind {
|
|||
; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
|
||||
; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
|
||||
; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
|
||||
; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 [M0]
|
||||
; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
|
||||
; GCN: s_endpgm
|
||||
define void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
|
||||
%gep = getelementptr i64 addrspace(3)* %ptr, i64 4
|
||||
|
|
|
|||
|
|
@ -30,9 +30,9 @@
|
|||
; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
|
||||
; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
|
||||
; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
|
||||
; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] [M0]
|
||||
; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] [M0]
|
||||
; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] offset:16 [M0]
|
||||
; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]]
|
||||
; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]]
|
||||
; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] offset:16
|
||||
|
||||
define void @local_memory_two_objects(i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@ declare i32 @llvm.r600.read.tidig.x() #1
|
|||
|
||||
; SI-LABEL: {{^}}load_shl_base_lds_0:
|
||||
; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
|
||||
; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 [M0]
|
||||
; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8
|
||||
; SI: s_endpgm
|
||||
define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
|
||||
%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -34,7 +34,7 @@ define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %ad
|
|||
|
||||
; SI-LABEL: {{^}}load_shl_base_lds_1:
|
||||
; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
|
||||
; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8 [M0]
|
||||
; SI: ds_read_b32 [[RESULT:v[0-9]+]], [[PTR]] offset:8
|
||||
; SI: v_add_i32_e32 [[ADDUSE:v[0-9]+]], 8, v{{[0-9]+}}
|
||||
; SI-DAG: buffer_store_dword [[RESULT]]
|
||||
; SI-DAG: buffer_store_dword [[ADDUSE]]
|
||||
|
|
@ -71,7 +71,7 @@ define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)
|
|||
; SI-LABEL: {{^}}load_shl_base_lds_2:
|
||||
; SI: s_mov_b32 m0, -1
|
||||
; SI-NEXT: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
|
||||
; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0]
|
||||
; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9
|
||||
; SI: s_endpgm
|
||||
define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {
|
||||
%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
@ -87,7 +87,7 @@ define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {
|
|||
|
||||
; SI-LABEL: {{^}}store_shl_base_lds_0:
|
||||
; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
|
||||
; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 [M0]
|
||||
; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8
|
||||
; SI: s_endpgm
|
||||
define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
|
||||
%tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
|
||||
|
|
|
|||
Loading…
Reference in New Issue