SimplifyCFG now predicts some conditional branches to true or false depending on previous branch on same comparison operands.
For example,
if (a == b) {
if (a > b) // this is false
Fixes some of the issues on <rdar://problem/10554090>
llvm-svn: 146822
This commit is contained in:
Pete Cooper
parent
3c2848ea31
commit
eadf124d2b
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@ -12,6 +12,7 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "simplifycfg"
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#include "llvm/Transforms/Utils/CmpInstAnalysis.h"
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#include "llvm/Transforms/Utils/Local.h"
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#include "llvm/Constants.h"
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#include "llvm/Instructions.h"
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@ -1702,6 +1703,47 @@ static bool SimplifyCondBranchToCondBranch(BranchInst *PBI, BranchInst *BI) {
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}
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}
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// Treat "if (cond1) { if (cond2) {} }" as "cond1 & cond2" and fold.
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// This gives us the value of what cond2 is given cond1 is already known to
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// be true.
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if (ICmpInst *LHS = dyn_cast<ICmpInst>(PBI->getCondition())) {
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if (ICmpInst *RHS = dyn_cast<ICmpInst>(BI->getCondition())) {
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ICmpInst::Predicate LHSCC = LHS->getPredicate(),
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RHSCC = RHS->getPredicate();
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if (PredicatesFoldable(LHSCC, RHSCC)) {
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if (LHS->getOperand(0) == RHS->getOperand(1) &&
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LHS->getOperand(1) == RHS->getOperand(0))
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LHS->swapOperands();
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if (LHS->getOperand(0) == RHS->getOperand(0) &&
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LHS->getOperand(1) == RHS->getOperand(1) &&
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BB->getSinglePredecessor()) {
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Value *Op0 = LHS->getOperand(0), *Op1 = LHS->getOperand(1);
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bool CondIsTrue = PBI->getSuccessor(0) == BB;
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unsigned LHSCode = getICmpCode(LHS, !CondIsTrue);
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unsigned RHSCode = getICmpCode(RHS);
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unsigned Code = LHSCode & RHSCode;
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Value *ConstantCondition = NULL;
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// If the resultant code is the same as the LHS code then as that
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// code is known to be true we can make RHS now be true.
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if (Code == LHSCode)
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ConstantCondition = ConstantInt::get(
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CmpInst::makeCmpResultType(LHS->getType()), 1);
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else {
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bool isSigned = LHS->isSigned() || RHS->isSigned();
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CmpInst::Predicate IgnoredNewPred;
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ConstantCondition = getICmpValue(isSigned, Code, Op0, Op1,
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IgnoredNewPred);
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}
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if (ConstantCondition) {
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RHS->replaceAllUsesWith(ConstantCondition);
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return true;
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}
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}
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}
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}
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}
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// If this is a conditional branch in an empty block, and if any
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// predecessors is a conditional branch to one of our destinations,
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// fold the conditions into logical ops and one cond br.
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@ -0,0 +1,152 @@
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; RUN: opt < %s -simplifycfg -dce -S | FileCheck %s
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; Test that when == is true, all 6 comparisons evaluate to true or false
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; ie, a == b implies a > b is false, but a >= b is true, and so on
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define void @testEqTrue(i32 %a, i32 %b) {
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; CHECK: @testEqTrue
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; CHECK: icmp eq i32 %a, %b
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; CHECK: call void @_Z1gi(i32 0)
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; a == b implies a == b
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; CHECK-NEXT: call void @_Z1gi(i32 1)
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; a == b implies a >= b
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; CHECK-NEXT: call void @_Z1gi(i32 3)
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; a == b implies a <= b
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; CHECK-NEXT: call void @_Z1gi(i32 4)
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; CHECK: ret void
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entry:
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%cmp = icmp eq i32 %a, %b
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br i1 %cmp, label %if.then, label %if.end18
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if.then: ; preds = %entry
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call void @_Z1gi(i32 0)
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%cmp1 = icmp eq i32 %a, %b
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br i1 %cmp1, label %if.then2, label %if.end
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if.then2: ; preds = %if.then
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call void @_Z1gi(i32 1)
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br label %if.end
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if.end: ; preds = %if.then2, %if.then
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%cmp3 = icmp ne i32 %a, %b
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br i1 %cmp3, label %if.then4, label %if.end5
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if.then4: ; preds = %if.end
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call void @_Z1gi(i32 2)
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br label %if.end5
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if.end5: ; preds = %if.then4, %if.end
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%cmp6 = icmp sge i32 %a, %b
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br i1 %cmp6, label %if.then7, label %if.end8
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if.then7: ; preds = %if.end5
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call void @_Z1gi(i32 3)
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br label %if.end8
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if.end8: ; preds = %if.then7, %if.end5
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%cmp9 = icmp sle i32 %a, %b
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br i1 %cmp9, label %if.then10, label %if.end11
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if.then10: ; preds = %if.end8
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call void @_Z1gi(i32 4)
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br label %if.end11
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if.end11: ; preds = %if.then10, %if.end8
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%cmp12 = icmp sgt i32 %a, %b
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br i1 %cmp12, label %if.then13, label %if.end14
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if.then13: ; preds = %if.end11
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call void @_Z1gi(i32 5)
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br label %if.end14
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if.end14: ; preds = %if.then13, %if.end11
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%cmp15 = icmp slt i32 %a, %b
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br i1 %cmp15, label %if.then16, label %if.end18
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if.then16: ; preds = %if.end14
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call void @_Z1gi(i32 6)
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br label %if.end18
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if.end18: ; preds = %if.end14, %if.then16, %entry
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ret void
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}
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; Test that when == is false, all 6 comparisons evaluate to true or false
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; ie, a == b implies a > b is false, but a >= b is true, and so on
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define void @testEqFalse(i32 %a, i32 %b) {
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; CHECK: @testEqFalse
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; CHECK: icmp eq i32 %a, %b
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; CHECK: call void @_Z1gi(i32 0)
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; CHECK-NOT: call void @_Z1gi(i32 1)
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; CHECK-NOT: icmp ne
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; CHECK: call void @_Z1gi(i32 2)
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; CHECK: icmp sge
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; CHECK: call void @_Z1gi(i32 3)
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; CHECK: icmp sle
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; CHECK: call void @_Z1gi(i32 4)
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; CHECK: icmp sgt
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; CHECK: call void @_Z1gi(i32 5)
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; CHECK: icmp slt
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; CHECK: call void @_Z1gi(i32 6)
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; CHECK: ret void
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entry:
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%cmp = icmp eq i32 %a, %b
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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call void @_Z1gi(i32 0)
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br label %if.end18
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if.else:
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%cmp1 = icmp eq i32 %a, %b
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br i1 %cmp1, label %if.then2, label %if.end
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if.then2: ; preds = %if.then
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call void @_Z1gi(i32 1)
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br label %if.end
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if.end: ; preds = %if.then2, %if.then
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%cmp3 = icmp ne i32 %a, %b
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br i1 %cmp3, label %if.then4, label %if.end5
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if.then4: ; preds = %if.end
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call void @_Z1gi(i32 2)
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br label %if.end5
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if.end5: ; preds = %if.then4, %if.end
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%cmp6 = icmp sge i32 %a, %b
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br i1 %cmp6, label %if.then7, label %if.end8
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if.then7: ; preds = %if.end5
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call void @_Z1gi(i32 3)
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br label %if.end8
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if.end8: ; preds = %if.then7, %if.end5
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%cmp9 = icmp sle i32 %a, %b
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br i1 %cmp9, label %if.then10, label %if.end11
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if.then10: ; preds = %if.end8
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call void @_Z1gi(i32 4)
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br label %if.end11
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if.end11: ; preds = %if.then10, %if.end8
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%cmp12 = icmp sgt i32 %a, %b
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br i1 %cmp12, label %if.then13, label %if.end14
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if.then13: ; preds = %if.end11
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call void @_Z1gi(i32 5)
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br label %if.end14
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if.end14: ; preds = %if.then13, %if.end11
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%cmp15 = icmp slt i32 %a, %b
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br i1 %cmp15, label %if.then16, label %if.end18
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if.then16: ; preds = %if.end14
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call void @_Z1gi(i32 6)
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br label %if.end18
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if.end18: ; preds = %if.end14, %if.then16, %entry
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ret void
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}
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declare void @_Z1gi(i32)
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