ARM sched model: Add integer VFP/SIMD instructions on Swift
Reapply 183269. llvm-svn: 183441
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Arnold Schwaighofer
parent
b4987e32fd
commit
eac54473dd
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@ -84,6 +84,9 @@ def WriteBrTbl : SchedWrite;
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// Fixpoint conversions.
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def WriteCvtFP : SchedWrite;
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// Noop.
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def WriteNoop : SchedWrite;
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// Define TII for use in SchedVariant Predicates.
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def : PredicateProlog<[{
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const ARMBaseInstrInfo *TII =
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@ -2541,4 +2541,5 @@ def : WriteRes<WriteBrL, [A9UnitB]>;
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def : WriteRes<WriteBrTbl, [A9UnitB]>;
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def : WriteRes<WritePreLd, []>;
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def : SchedAlias<WriteCvtFP, A9WriteF>;
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def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
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} // SchedModel = CortexA9Model
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@ -1554,10 +1554,131 @@ let SchedModel = SwiftModel in {
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def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
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def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; }
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// 4.2.27 Not issued
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def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
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def : InstRW<[WriteNoop], (instregex "t2IT", "IT", "NOP")>;
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// 4.2.28 Advanced SIMD, Integer, 2 cycle
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def : InstRW<[SwiftWriteP0TwoCycle],
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(instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
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"VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi",
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"VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
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"VSHL", "VSHR(s|u)", "VSHLL", "VQSHL", "VQSHLU", "VBIF",
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"VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
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def : InstRW<[SwiftWriteP1TwoCycle],
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(instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
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// 4.2.29 Advanced SIMD, Integer, 4 cycle
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// 4.2.30 Advanced SIMD, Integer with Accumulate
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def : InstRW<[SwiftWriteP0FourCycle],
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(instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
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"VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
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"VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD",
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"VQSUB")>;
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def : InstRW<[SwiftWriteP1FourCycle],
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(instregex "VRECPE", "VRSQRTE")>;
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// 4.2.31 Advanced SIMD, Add and Shift with Narrow
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def : InstRW<[SwiftWriteP0P1FourCycle],
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(instregex "VADDHN", "VSUBHN", "VSHRN")>;
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def : InstRW<[SwiftWriteP0P1SixCycle],
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(instregex "VRADDHN", "VRSUBHN", "VRSHRN", "VQSHRN", "VQSHRUN",
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"VQRSHRN", "VQRSHRUN")>;
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// 4.2.32 Advanced SIMD, Vector Table Lookup
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foreach Num = 1-4 in {
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def SwiftWrite#Num#xP1TwoCycle : WriteSequence<[SwiftWriteP1TwoCycle], Num>;
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}
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def : InstRW<[SwiftWrite1xP1TwoCycle],
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(instregex "VTB(L|X)1")>;
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def : InstRW<[SwiftWrite2xP1TwoCycle],
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(instregex "VTB(L|X)2")>;
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def : InstRW<[SwiftWrite3xP1TwoCycle],
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(instregex "VTB(L|X)3")>;
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def : InstRW<[SwiftWrite4xP1TwoCycle],
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(instregex "VTB(L|X)4")>;
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// 4.2.33 Advanced SIMD, Transpose
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def : InstRW<[SwiftWriteP1FourCycle, SwiftWriteP1FourCycle,
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SwiftWriteP1TwoCycle/*RsrcOnly*/, SchedReadAdvance<2>],
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(instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
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// 4.2.34 Advanced SIMD and VFP, Floating Point
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def : InstRW<[SwiftWriteP0TwoCycle], (instregex "VABS(S|D)$", "VNEG(S|D)$")>;
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def : InstRW<[SwiftWriteP0FourCycle],
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(instregex "VCMP(D|S|ZD|ZS)$", "VCMPE(D|S|ZD|ZS)")>;
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def : InstRW<[SwiftWriteP0FourCycle],
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(instregex "VADD(S|f)", "VSUB(S|f)", "VABD", "VPADDf", "VMAX", "VMIN", "VPMAX",
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"VPMIN")>;
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def : InstRW<[SwiftWriteP0SixCycle], (instregex "VADDD$", "VSUBD$")>;
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def : InstRW<[SwiftWriteP1EightCycle], (instregex "VRECPS", "VRSQRTS")>;
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// 4.2.35 Advanced SIMD and VFP, Multiply
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def : InstRW<[SwiftWriteP1FourCycle],
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(instregex "VMUL(S|v|p|f|s)", "VNMULS", "VQDMULH", "VQRDMULH",
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"VMULL", "VQDMULL")>;
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def : InstRW<[SwiftWriteP1SixCycle],
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(instregex "VMULD", "VNMULD")>;
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def : InstRW<[SwiftWriteP1FourCycle],
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(instregex "VMLA", "VMLS", "VNMLA", "VNMLS", "VFMA(S|D)", "VFMS(S|D)",
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"VFNMA", "VFNMS", "VMLAL", "VMLSL","VQDMLAL", "VQDMLSL")>;
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def : InstRW<[SwiftWriteP1EightCycle], (instregex "VFMAfd", "VFMSfd")>;
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def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>;
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// 4.2.36 Advanced SIMD and VFP, Convert
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def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
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// Fixpoint conversions.
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def : WriteRes<WriteCvtFP, [SwiftUnitP1]> { let Latency = 4; }
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// 4.2.37 Advanced SIMD and VFP, Move
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def : InstRW<[SwiftWriteP0TwoCycle],
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(instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc",
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"VMVNv", "VMVN(d|q)", "VMVN(S|D)cc",
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"FCONST(D|S)")>;
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def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>;
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def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
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(instregex "VQMOVN")>;
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def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN", "VDUPf")>;
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def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
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(instregex "VDUP(8|16|32)")>;
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def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>;
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def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
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(instregex "VMOVSR$", "VSETLN")>;
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def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle],
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(instregex "VMOVRR(D|S)$")>;
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def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;
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def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>,
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WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle,
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SwiftWriteP1TwoCycle]>],
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(instregex "VMOVSRR$")>;
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def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle]>],
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(instregex "VGETLN(u|i)")>;
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def : InstRW<[WriteSequence<[SwiftWriteP1TwoCycle, SwiftWriteP2ThreeCycle,
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SwiftWriteP01OneCycle]>],
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(instregex "VGETLNs")>;
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// 4.2.38 Advanced SIMD and VFP, Move FPSCR
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// Serializing instructions.
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def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
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let Latency = 15;
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let ResourceCycles = [15];
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}
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def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
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let Latency = 15;
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let ResourceCycles = [15];
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}
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def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
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let Latency = 15;
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let ResourceCycles = [15];
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}
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def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
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(instregex "VMRS")>;
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def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
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(instregex "VMSR")>;
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// Not serializing.
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def : InstRW<[SwiftWriteP0TwoCycle], (instregex "FMSTAT")>;
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// Preload.
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def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
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let ResourceCycles = [0];
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