Implement ctlz and cttz with bsr and bsf.
llvm-svn: 45024
This commit is contained in:
Evan Cheng
parent
d4d8c3c717
commit
e9fbc3f014
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@ -210,18 +210,18 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
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setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
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}
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setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
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@ -5345,6 +5345,42 @@ SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
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ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
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}
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SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType OpVT = VT;
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unsigned NumBits = MVT::getSizeInBits(VT);
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Op = Op.getOperand(0);
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if (VT == MVT::i8) {
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OpVT = MVT::i32;
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Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
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}
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if (VT == MVT::i32 || VT == MVT::i64)
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return DAG.getNode(ISD::XOR, OpVT, DAG.getNode(X86ISD::BSR, OpVT, Op),
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DAG.getConstant(NumBits-1, OpVT));
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Op = DAG.getNode(ISD::SUB, OpVT, DAG.getConstant(NumBits-1, OpVT),
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DAG.getNode(X86ISD::BSR, OpVT, Op));
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if (VT == MVT::i8)
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Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
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return Op;
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}
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SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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MVT::ValueType OpVT = VT;
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Op = Op.getOperand(0);
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if (VT == MVT::i8) {
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OpVT = MVT::i32;
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Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
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}
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Op = DAG.getNode(X86ISD::BSF, OpVT, Op);
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if (VT == MVT::i8)
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Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
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return Op;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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@ -5387,7 +5423,8 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
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case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
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case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
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case ISD::CTLZ: return LowerCTLZ(Op, DAG);
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case ISD::CTTZ: return LowerCTTZ(Op, DAG);
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// FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
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case ISD::READCYCLECOUNTER:
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@ -5407,6 +5444,8 @@ SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
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const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return NULL;
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case X86ISD::BSF: return "X86ISD::BSF";
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case X86ISD::BSR: return "X86ISD::BSR";
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case X86ISD::SHLD: return "X86ISD::SHLD";
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case X86ISD::SHRD: return "X86ISD::SHRD";
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case X86ISD::FAND: return "X86ISD::FAND";
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@ -28,6 +28,11 @@ namespace llvm {
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// Start the numbering where the builtin ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+X86::INSTRUCTION_LIST_END,
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/// BSF - Bit scan forward.
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/// BSR - Bit scan reverse.
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BSF,
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BSR,
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/// SHLD, SHRD - Double shift instructions. These correspond to
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/// X86::SHLDxx and X86::SHRDxx instructions.
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SHLD,
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@ -489,6 +494,8 @@ namespace llvm {
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SDOperand LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerTRAMPOLINE(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTLZ(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerCTTZ(SDOperand Op, SelectionDAG &DAG);
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SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
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};
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@ -57,6 +57,8 @@ def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
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def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>;
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def X86bsf : SDNode<"X86ISD::BSF", SDTIntUnaryOp>;
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def X86bsr : SDNode<"X86ISD::BSR", SDTIntUnaryOp>;
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def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
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def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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@ -445,6 +447,35 @@ def XCHG32rm : I<0x87, MRMSrcMem,
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(outs), (ins GR32:$src1, i32mem:$src2),
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"xchg{l}\t{$src2|$src1}, {$src1|$src2}", []>;
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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def BSF16rr : I<0xBC, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
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"bsf{w}\t{$src, $dst||$dst, $src}",
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[(set GR16:$dst, (X86bsf GR16:$src))]>, TB;
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def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"bsf{w}\t{$src, $dst||$dst, $src}",
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[(set GR16:$dst, (X86bsf (loadi16 addr:$src)))]>, TB;
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def BSF32rr : I<0xBC, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
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"bsf{l}\t{$src, $dst||$dst, $src}",
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[(set GR32:$dst, (X86bsf GR32:$src))]>, TB;
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def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"bsf{l}\t{$src, $dst||$dst, $src}",
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[(set GR32:$dst, (X86bsf (loadi32 addr:$src)))]>, TB;
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def BSR16rr : I<0xBD, AddRegFrm, (outs GR16:$dst), (ins GR16:$src),
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"bsr{w}\t{$src, $dst||$dst, $src}",
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[(set GR16:$dst, (X86bsr GR16:$src))]>, TB;
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def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"bsr{w}\t{$src, $dst||$dst, $src}",
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[(set GR16:$dst, (X86bsr (loadi16 addr:$src)))]>, TB;
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def BSR32rr : I<0xBD, AddRegFrm, (outs GR32:$dst), (ins GR32:$src),
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"bsr{l}\t{$src, $dst||$dst, $src}",
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[(set GR32:$dst, (X86bsr GR32:$src))]>, TB;
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def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"bsr{l}\t{$src, $dst||$dst, $src}",
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[(set GR32:$dst, (X86bsr (loadi32 addr:$src)))]>, TB;
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} // Defs = [EFLAGS]
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def LEA16r : I<0x8D, MRMSrcMem,
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(outs GR16:$dst), (ins i32mem:$src),
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"lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
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@ -167,6 +167,23 @@ def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
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def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
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"xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
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// Bit scan instructions.
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let Defs = [EFLAGS] in {
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def BSF64rr : RI<0xBC, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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"bsf{q}\t{$src, $dst||$dst, $src}",
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[(set GR64:$dst, (X86bsf GR64:$src))]>, TB;
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def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsf{q}\t{$src, $dst||$dst, $src}",
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[(set GR64:$dst, (X86bsf (loadi64 addr:$src)))]>, TB;
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def BSR64rr : RI<0xBD, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
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"bsr{q}\t{$src, $dst||$dst, $src}",
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[(set GR64:$dst, (X86bsr GR64:$src))]>, TB;
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def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
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"bsr{q}\t{$src, $dst||$dst, $src}",
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[(set GR64:$dst, (X86bsr (loadi64 addr:$src)))]>, TB;
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} // Defs = [EFLAGS]
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// Repeat string ops
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let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
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def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
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@ -0,0 +1,16 @@
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; RUN: llvm-as < %s | llc -march=x86 | grep bsr
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; RUN: llvm-as < %s | llc -march=x86 | grep bsf
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define i32 @t1(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
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ret i32 %tmp
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}
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declare i32 @llvm.ctlz.i32(i32) nounwind readnone
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define i32 @t2(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
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ret i32 %tmp
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}
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declare i32 @llvm.cttz.i32(i32) nounwind readnone
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