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Simplify extract element based on comments from Duncan Sands. 

llvm-svn: 62459
This commit is contained in:
Mon P Wang 2009-01-18 06:43:40 +00:00
parent b699c9bf57
commit e9e7abb6b8
1 changed files with 3 additions and 7 deletions
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8
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4880,14 +4880,9 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// (vextract (scalar_to_vector val, 0) -> val // (vextract (scalar_to_vector val, 0) -> val
SDValue InVec = N->getOperand(0); SDValue InVec = N->getOperand(0);
SDValue EltNo = N->getOperand(1);
if (isa<ConstantSDNode>(EltNo)) { if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR)
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && Elt == 0) {
return InVec.getOperand(0); return InVec.getOperand(0);
}
}
// Perform only after legalization to ensure build_vector / vector_shuffle // Perform only after legalization to ensure build_vector / vector_shuffle
// optimizations have already been done. // optimizations have already been done.
@ -4896,6 +4891,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
SDValue EltNo = N->getOperand(1);
if (isa<ConstantSDNode>(EltNo)) { if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();