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TableGen SubtargetEmitter fix to allow A9 and Swift to coexist. 

Allow variants to be defined only for some processors on a target.

llvm-svn: 178074
This commit is contained in:
Andrew Trick 2013-03-26 21:36:39 +00:00
parent 1fa2f945ea
commit e97978f94c
2 changed files with 24 additions and 2 deletions
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9
llvm/utils/TableGen/CodeGenSchedule.cpp
View File

@ -1308,7 +1308,7 @@ void CodeGenSchedModels::inferFromRW(const IdxVec &OperWrites,
const IdxVec &OperReads,
unsigned FromClassIdx,
const IdxVec &ProcIndices) {
DEBUG(dbgs() << "INFER RW: ");
DEBUG(dbgs() << "INFER RW proc("; dumpIdxVec(ProcIndices); dbgs() << ") ");
// Create a seed transition with an empty PredTerm and the expanded sequences
// of SchedWrites for the current SchedClass.
@ -1650,6 +1650,13 @@ void CodeGenSchedClass::dump(const CodeGenSchedModels* SchedModels) const {
}
}
dbgs() << "\n ProcIdx: "; dumpIdxVec(ProcIndices); dbgs() << '\n';
if (!Transitions.empty()) {
dbgs() << "\n Transitions for Proc ";
for (std::vector<CodeGenSchedTransition>::const_iterator
TI = Transitions.begin(), TE = Transitions.end(); TI != TE; ++TI) {
dumpIdxVec(TI->ProcIndices);
}
}
}
void PredTransitions::dump() const {

17
llvm/utils/TableGen/SubtargetEmitter.cpp
View File

@ -850,7 +850,22 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
SCDesc.ReadAdvanceIdx = 0;
// A Variant SchedClass has no resources of its own.
if (!SCI->Transitions.empty()) {
bool HasVariants = false;
for (std::vector<CodeGenSchedTransition>::const_iterator
TI = SCI->Transitions.begin(), TE = SCI->Transitions.end();
TI != TE; ++TI) {
if (TI->ProcIndices[0] == 0) {
HasVariants = true;
break;
}
IdxIter PIPos = std::find(TI->ProcIndices.begin(),
TI->ProcIndices.end(), ProcModel.Index);
if (PIPos != TI->ProcIndices.end()) {
HasVariants = true;
break;
}
}
if (HasVariants) {
SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
continue;
}