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AMDGPU: s[102:103] is unavailable on VI 

llvm-svn: 252000
This commit is contained in:
Matt Arsenault 2015-11-03 22:39:52 +00:00
parent 192b282bf3
commit e8ed13d946
1 changed files with 10 additions and 1 deletions
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11
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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@ -45,9 +45,18 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// will physically contain VCC.
reserveRegisterTuples(Reserved, AMDGPU::SGPR102_SGPR103);
const AMDGPUSubtarget &ST = MF.getSubtarget<AMDGPUSubtarget>();
if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
// SI/CI have 104 SGPRs. VI has 102. We need to shift down the reservation
// for VCC/FLAT_SCR.
reserveRegisterTuples(Reserved, AMDGPU::SGPR98_SGPR99);
reserveRegisterTuples(Reserved, AMDGPU::SGPR100_SGPR101);
}
// Tonga and Iceland can only allocate a fixed number of SGPRs due
// to a hw bug.
if (MF.getSubtarget<AMDGPUSubtarget>().hasSGPRInitBug()) {
if (ST.hasSGPRInitBug()) {
unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
// Reserve some SGPRs for FLAT_SCRATCH and VCC (4 SGPRs).
// Assume XNACK_MASK is unused.