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Revert r109901. The implementation of <rdar://problem/7405933> (r110423) doesn't 

need the Compare flag after all.

--- Reverse-merging r109901 into '.':
U    include/llvm/Target/TargetInstrDesc.h
U    include/llvm/Target/Target.td
U    utils/TableGen/InstrInfoEmitter.cpp
U    utils/TableGen/CodeGenInstruction.cpp
U    utils/TableGen/CodeGenInstruction.h

llvm-svn: 110424
This commit is contained in:
Bill Wendling 2010-08-06 01:36:09 +00:00
parent 7de9d52c13
commit e8bb340203
5 changed files with 1 additions and 11 deletions
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1
llvm/include/llvm/Target/Target.td
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@ -198,7 +198,6 @@ class Instruction {
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isCompare = 0; // Is this instruction a comparison instruction?
bit isBarrier = 0; // Can control flow fall through this instruction?
bit isCall = 0; // Is this instruction a call instruction?
bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?

8
llvm/include/llvm/Target/TargetInstrDesc.h
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@ -105,7 +105,6 @@ namespace TID {
IndirectBranch,
Predicable,
NotDuplicable,
Compare,
DelaySlot,
FoldableAsLoad,
MayLoad,
@ -316,7 +315,7 @@ public:
bool isIndirectBranch() const {
return Flags & (1 << TID::IndirectBranch);
}
/// isConditionalBranch - Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
/// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
@ -341,11 +340,6 @@ public:
return Flags & (1 << TID::Predicable);
}
/// isCompare - Return true if this instruction is a comparison.
bool isCompare() const {
return Flags & (1 << TID::Compare);
}
/// isNotDuplicable - Return true if this instruction cannot be safely
/// duplicated. For example, if the instruction has a unique labels attached
/// to it, duplicating it would cause multiple definition errors.

1
llvm/utils/TableGen/CodeGenInstruction.cpp
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@ -102,7 +102,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isReturn = R->getValueAsBit("isReturn");
isBranch = R->getValueAsBit("isBranch");
isIndirectBranch = R->getValueAsBit("isIndirectBranch");
isCompare = R->getValueAsBit("isCompare");
isBarrier = R->getValueAsBit("isBarrier");
isCall = R->getValueAsBit("isCall");
canFoldAsLoad = R->getValueAsBit("canFoldAsLoad");

1
llvm/utils/TableGen/CodeGenInstruction.h
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@ -123,7 +123,6 @@ namespace llvm {
bool isReturn;
bool isBranch;
bool isIndirectBranch;
bool isCompare;
bool isBarrier;
bool isCall;
bool canFoldAsLoad;

1
llvm/utils/TableGen/InstrInfoEmitter.cpp
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@ -270,7 +270,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isReturn) OS << "|(1<<TID::Return)";
if (Inst.isBranch) OS << "|(1<<TID::Branch)";
if (Inst.isIndirectBranch) OS << "|(1<<TID::IndirectBranch)";
if (Inst.isCompare) OS << "|(1<<TID::Compare)";
if (Inst.isBarrier) OS << "|(1<<TID::Barrier)";
if (Inst.hasDelaySlot) OS << "|(1<<TID::DelaySlot)";
if (Inst.isCall) OS << "|(1<<TID::Call)";