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[AMDGPU] performMinMaxCombine should not optimize patterns of vectors to min3/max3. 

Summary: There are no packed instructions for min3 or max3. So, performMinMaxCombine should not optimize vectors of f16 to min3/max3.

Author: FarhanaAleen

Reviewed By: arsenm

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D45219

llvm-svn: 329131
This commit is contained in:
Farhana Aleen 2018-04-03 23:00:30 +00:00
parent 6b8d8f4010
commit e80aeac0f2
3 changed files with 59 additions and 1 deletions
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2
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -6446,7 +6446,7 @@ SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY &&
VT != MVT::f64 &&
!VT.isVector() && VT != MVT::f64 &&
((VT != MVT::f16 && VT != MVT::i16) || Subtarget->hasMin3Max3_16())) {
// max(max(a, b), c) -> max3(a, b, c)
// min(min(a, b), c) -> min3(a, b, c)

29
llvm/test/CodeGen/AMDGPU/fmax3.ll
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@ -84,9 +84,38 @@ define amdgpu_kernel void @test_fmax3_olt_1_f16(half addrspace(1)* %out, half ad
ret void
}
; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of max3
; since there are no pack instructions for fmax3.
; GCN-LABEL: {{^}}no_fmax3_v2f16:
; SI: v_cvt_f16_f32_e32
; SI: v_max_f32_e32
; SI-NEXT: v_max_f32_e32
; SI-NEXT: v_max3_f32
; SI-NEXT: v_max3_f32
; VI: v_max_f16_e32
; VI-NEXT: v_max_f16_e32
; VI-NEXT: v_max_f16_e32
; VI-NEXT: v_max_f16_e32
; VI-NEXT: v_max_f16_e32
; VI-NEXT: v_max_f16_e32
; GFX9: v_pk_max_f16
; GFX9-NEXT: v_pk_max_f16
; GFX9-NEXT: v_pk_max_f16
define <2 x half> @no_fmax3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
entry:
%max = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
%max1 = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %c, <2 x half> %max)
%res = tail call fast <2 x half> @llvm.maxnum.v2f16(<2 x half> %max1, <2 x half> %d)
ret <2 x half> %res
}
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.maxnum.f32(float, float) #1
declare half @llvm.maxnum.f16(half, half) #1
declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone speculatable }

29
llvm/test/CodeGen/AMDGPU/fmin3.ll
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@ -82,9 +82,38 @@ define amdgpu_kernel void @test_fmin3_olt_1_f16(half addrspace(1)* %out, half ad
ret void
}
; Checks whether the test passes; performMinMaxCombine() should not optimize vector patterns of min3
; since there are no pack instructions for fmin3.
; GCN-LABEL: {{^}}no_fmin3_v2f16:
; SI: v_cvt_f16_f32_e32
; SI: v_min_f32_e32
; SI-NEXT: v_min_f32_e32
; SI-NEXT: v_min3_f32
; SI-NEXT: v_min3_f32
; VI: v_min_f16_e32
; VI-NEXT: v_min_f16_e32
; VI-NEXT: v_min_f16_e32
; VI-NEXT: v_min_f16_e32
; VI-NEXT: v_min_f16_e32
; VI-NEXT: v_min_f16_e32
; GFX9: v_pk_min_f16
; GFX9: v_pk_min_f16
; GFX9: v_pk_min_f16
define <2 x half> @no_fmin3_v2f16(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) {
entry:
%min = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
%min1 = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %c, <2 x half> %min)
%res = tail call fast <2 x half> @llvm.minnum.v2f16(<2 x half> %min1, <2 x half> %d)
ret <2 x half> %res
}
declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @llvm.minnum.f32(float, float) #1
declare half @llvm.minnum.f16(half, half) #1
declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
attributes #0 = { nounwind }
attributes #1 = { nounwind readnone speculatable }