[Power9] Implement new vector compare, extract, insert instructions
This change implements the following vector operations:
- Vector Compare Not Equal
- vcmpneb(.) vcmpneh(.) vcmpnew(.)
- vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
- Vector Extract Unsigned
- vextractub vextractuh vextractuw vextractd
- vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
- Vector Insert
- vinsertb vinserth vinsertw vinsertd
26 instructions.
Phabricator: http://reviews.llvm.org/D15916
llvm-svn: 262392
This commit is contained in:
Kit Barton
parent
18988ae66c
commit
e725669483
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@ -1213,3 +1213,68 @@ def VNCIPHERLAST : VX1_Int_Ty<1353, "vncipherlast",
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int_ppc_altivec_crypto_vncipherlast, v2i64>;
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def VSBOX : VXBX_Int_Ty<1480, "vsbox", int_ppc_altivec_crypto_vsbox, v2i64>;
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} // HasP8Crypto
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// The following altivec instructions were introduced in Power ISA 3.0
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def HasP9Altivec : Predicate<"PPCSubTarget->hasP9Altivec()">;
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let Predicates = [HasP9Altivec] in {
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// Vector Compare Not Equal (Zero)
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class P9VCMP<bits<10> xo, string asmstr, ValueType Ty>
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: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
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IIC_VecFPCompare, []>;
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class P9VCMPo<bits<10> xo, string asmstr, ValueType Ty>
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: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
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IIC_VecFPCompare, []> {
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let Defs = [CR6];
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let RC = 1;
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}
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// i8 element comparisons.
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def VCMPNEB : P9VCMP < 7, "vcmpneb $vD, $vA, $vB" , v16i8>;
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def VCMPNEBo : P9VCMPo< 7, "vcmpneb. $vD, $vA, $vB" , v16i8>;
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def VCMPNEZB : P9VCMP <263, "vcmpnezb $vD, $vA, $vB" , v16i8>;
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def VCMPNEZBo : P9VCMPo<263, "vcmpnezb. $vD, $vA, $vB", v16i8>;
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// i16 element comparisons.
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def VCMPNEH : P9VCMP < 71, "vcmpneh $vD, $vA, $vB" , v8i16>;
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def VCMPNEHo : P9VCMPo< 71, "vcmpneh. $vD, $vA, $vB" , v8i16>;
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def VCMPNEZH : P9VCMP <327, "vcmpnezh $vD, $vA, $vB" , v8i16>;
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def VCMPNEZHo : P9VCMPo<327, "vcmpnezh. $vD, $vA, $vB", v8i16>;
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// i32 element comparisons.
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def VCMPNEW : P9VCMP <135, "vcmpnew $vD, $vA, $vB" , v4i32>;
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def VCMPNEWo : P9VCMPo<135, "vcmpnew. $vD, $vA, $vB" , v4i32>;
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def VCMPNEZW : P9VCMP <391, "vcmpnezw $vD, $vA, $vB" , v4i32>;
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def VCMPNEZWo : P9VCMPo<391, "vcmpnezw. $vD, $vA, $vB", v4i32>;
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// VX-Form: [PO VRT / UIM VRB XO].
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// We use VXForm_1 to implement it, that is, we use "VRA" (5 bit) to represent
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// "/ UIM" (1 + 4 bit)
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class VX1_VT5_UIM5_VB5<bits<11> xo, string opc, list<dag> pattern>
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: VXForm_1<xo, (outs vrrc:$vD), (ins u4imm:$UIMM, vrrc:$vB),
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!strconcat(opc, " $vD, $vB, $UIMM"), IIC_VecGeneral, pattern>;
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class VX1_RT5_RA5_VB5<bits<11> xo, string opc, list<dag> pattern>
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: VXForm_1<xo, (outs g8rc:$rD), (ins g8rc:$rA, vrrc:$vB),
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!strconcat(opc, " $rD, $rA, $vB"), IIC_VecGeneral, pattern>;
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// Vector Extract Unsigned
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def VEXTRACTUB : VX1_VT5_UIM5_VB5<525, "vextractub", []>;
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def VEXTRACTUH : VX1_VT5_UIM5_VB5<589, "vextractuh", []>;
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def VEXTRACTUW : VX1_VT5_UIM5_VB5<653, "vextractuw", []>;
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def VEXTRACTD : VX1_VT5_UIM5_VB5<717, "vextractd" , []>;
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// Vector Extract Unsigned Byte/Halfword/Word Left/Right-Indexed
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def VEXTUBLX : VX1_RT5_RA5_VB5<1549, "vextublx", []>;
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def VEXTUBRX : VX1_RT5_RA5_VB5<1805, "vextubrx", []>;
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def VEXTUHLX : VX1_RT5_RA5_VB5<1613, "vextuhlx", []>;
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def VEXTUHRX : VX1_RT5_RA5_VB5<1869, "vextuhrx", []>;
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def VEXTUWLX : VX1_RT5_RA5_VB5<1677, "vextuwlx", []>;
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def VEXTUWRX : VX1_RT5_RA5_VB5<1933, "vextuwrx", []>;
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// Vector Insert Element Instructions
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def VINSERTB : VX1_VT5_UIM5_VB5<781, "vinsertb", []>;
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def VINSERTH : VX1_VT5_UIM5_VB5<845, "vinserth", []>;
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def VINSERTW : VX1_VT5_UIM5_VB5<909, "vinsertw", []>;
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def VINSERTD : VX1_VT5_UIM5_VB5<973, "vinsertd", []>;
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} // end HasP9Altivec
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@ -3,6 +3,37 @@
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TODO: Instructions Need Implement Instrinstics or Map to LLVM IR
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Altivec:
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- Vector Compare Not Equal (Zero):
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vcmpneb(.) vcmpneh(.) vcmpnew(.)
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vcmpnezb(.) vcmpnezh(.) vcmpnezw(.)
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. Same as other VCMP*, use VCMP/VCMPo form (support intrinsic)
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- Vector Extract Unsigned: vextractub vextractuh vextractuw vextractd
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. Don't use llvm extractelement because they have different semantics
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. Use instrinstics:
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(set v2i64:$vD, (int_ppc_altivec_vextractub v16i8:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractuh v8i16:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractuw v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vextractd v2i64:$vA, imm:$UIMM))
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- Vector Extract Unsigned Byte Left/Right-Indexed:
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vextublx vextubrx vextuhlx vextuhrx vextuwlx vextuwrx
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. Use instrinstics:
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// Left-Indexed
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(set i64:$rD, (int_ppc_altivec_vextublx i64:$rA, v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuhlx i64:$rA, v8i16:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuwlx i64:$rA, v4i32:$vB))
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// Right-Indexed
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(set i64:$rD, (int_ppc_altivec_vextubrx i64:$rA, v16i8:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuhrx i64:$rA, v8i16:$vB))
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(set i64:$rD, (int_ppc_altivec_vextuwrx i64:$rA, v4i32:$vB))
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- Vector Insert Element Instructions: vinsertb vinsertd vinserth vinsertw
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(set v16i8:$vD, (int_ppc_altivec_vinsertb v16i8:$vA, imm:$UIMM))
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(set v8i16:$vD, (int_ppc_altivec_vinsertd v8i16:$vA, imm:$UIMM))
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(set v4i32:$vD, (int_ppc_altivec_vinserth v4i32:$vA, imm:$UIMM))
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(set v2i64:$vD, (int_ppc_altivec_vinsertw v2i64:$vA, imm:$UIMM))
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VSX:
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@ -672,3 +672,83 @@
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# CHECK: mfvscr 2
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0x10 0x40 0x06 0x04
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# Power9 instructions
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# CHECK: vcmpneb 2, 3, 4
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0x10 0x43 0x20 0x07
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# CHECK: vcmpneb. 2, 3, 4
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0x10 0x43 0x24 0x07
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# CHECK: vcmpnezb 2, 3, 4
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0x10 0x43 0x21 0x07
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# CHECK: vcmpnezb. 2, 3, 4
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0x10 0x43 0x25 0x07
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# CHECK: vcmpneh 2, 3, 4
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0x10 0x43 0x20 0x47
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# CHECK: vcmpneh. 2, 3, 4
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0x10 0x43 0x24 0x47
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# CHECK: vcmpnezh 2, 3, 4
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0x10 0x43 0x21 0x47
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# CHECK: vcmpnezh. 2, 3, 4
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0x10 0x43 0x25 0x47
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# CHECK: vcmpnew 2, 3, 4
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0x10 0x43 0x20 0x87
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# CHECK: vcmpnew. 2, 3, 4
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0x10 0x43 0x24 0x87
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# CHECK: vcmpnezw 2, 3, 4
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0x10 0x43 0x21 0x87
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# CHECK: vcmpnezw. 2, 3, 4
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0x10 0x43 0x25 0x87
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# CHECK: vextractub 2, 3, 15
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0x10 0x4f 0x1a 0x0d
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# CHECK: vextractuh 2, 3, 14
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0x10 0x4e 0x1a 0x4d
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# CHECK: vextractuw 2, 3, 12
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0x10 0x4c 0x1a 0x8d
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# CHECK: vextractd 2, 3, 8
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0x10 0x48 0x1a 0xcd
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# CHECK: vextublx 2, 3, 4
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0x10 0x43 0x26 0x0d
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# CHECK: vextubrx 2, 3, 4
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0x10 0x43 0x27 0x0d
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# CHECK: vextuhlx 2, 3, 4
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0x10 0x43 0x26 0x4d
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# CHECK: vextuhrx 2, 3, 4
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0x10 0x43 0x27 0x4d
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# CHECK: vextuwlx 2, 3, 4
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0x10 0x43 0x26 0x8d
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# CHECK: vextuwrx 2, 3, 4
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0x10 0x43 0x27 0x8d
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# CHECK: vinsertb 2, 3, 15
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0x10 0x4f 0x1b 0x0d
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# CHECK: vinserth 2, 3, 14
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0x10 0x4e 0x1b 0x4d
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# CHECK: vinsertw 2, 3, 12
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0x10 0x4c 0x1b 0x8d
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# CHECK: vinsertd 2, 3, 8
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0x10 0x48 0x1b 0xcd
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@ -742,3 +742,91 @@
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# CHECK-LE: mfvscr 2 # encoding: [0x04,0x06,0x40,0x10]
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mfvscr 2
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# Power9 instructions
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# Vector Compare Not Equal (Zero)
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# CHECK-BE: vcmpneb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x07]
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# CHECK-LE: vcmpneb 2, 3, 4 # encoding: [0x07,0x20,0x43,0x10]
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vcmpneb 2, 3, 4
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# CHECK-BE: vcmpneb. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x07]
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# CHECK-LE: vcmpneb. 2, 3, 4 # encoding: [0x07,0x24,0x43,0x10]
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vcmpneb. 2, 3, 4
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# CHECK-BE: vcmpnezb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x07]
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# CHECK-LE: vcmpnezb 2, 3, 4 # encoding: [0x07,0x21,0x43,0x10]
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vcmpnezb 2, 3, 4
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# CHECK-BE: vcmpnezb. 2, 3, 4 # encoding: [0x10,0x43,0x25,0x07]
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# CHECK-LE: vcmpnezb. 2, 3, 4 # encoding: [0x07,0x25,0x43,0x10]
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vcmpnezb. 2, 3, 4
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# CHECK-BE: vcmpneh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x47]
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# CHECK-LE: vcmpneh 2, 3, 4 # encoding: [0x47,0x20,0x43,0x10]
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vcmpneh 2, 3, 4
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# CHECK-BE: vcmpneh. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x47]
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# CHECK-LE: vcmpneh. 2, 3, 4 # encoding: [0x47,0x24,0x43,0x10]
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vcmpneh. 2, 3, 4
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# CHECK-BE: vcmpnezh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x47]
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# CHECK-LE: vcmpnezh 2, 3, 4 # encoding: [0x47,0x21,0x43,0x10]
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vcmpnezh 2, 3, 4
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# CHECK-BE: vcmpnezh. 2, 3, 4 # encoding: [0x10,0x43,0x25,0x47]
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# CHECK-LE: vcmpnezh. 2, 3, 4 # encoding: [0x47,0x25,0x43,0x10]
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vcmpnezh. 2, 3, 4
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# CHECK-BE: vcmpnew 2, 3, 4 # encoding: [0x10,0x43,0x20,0x87]
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# CHECK-LE: vcmpnew 2, 3, 4 # encoding: [0x87,0x20,0x43,0x10]
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vcmpnew 2, 3, 4
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# CHECK-BE: vcmpnew. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x87]
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# CHECK-LE: vcmpnew. 2, 3, 4 # encoding: [0x87,0x24,0x43,0x10]
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vcmpnew. 2, 3, 4
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# CHECK-BE: vcmpnezw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x87]
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# CHECK-LE: vcmpnezw 2, 3, 4 # encoding: [0x87,0x21,0x43,0x10]
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vcmpnezw 2, 3, 4
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# CHECK-BE: vcmpnezw. 2, 3, 4 # encoding: [0x10,0x43,0x25,0x87]
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# CHECK-LE: vcmpnezw. 2, 3, 4 # encoding: [0x87,0x25,0x43,0x10]
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vcmpnezw. 2, 3, 4
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# Vector Extract Unsigned
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# CHECK-BE: vextractub 2, 3, 15 # encoding: [0x10,0x4f,0x1a,0x0d]
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# CHECK-LE: vextractub 2, 3, 15 # encoding: [0x0d,0x1a,0x4f,0x10]
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vextractub 2, 3, 15
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# CHECK-BE: vextractuh 2, 3, 14 # encoding: [0x10,0x4e,0x1a,0x4d]
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# CHECK-LE: vextractuh 2, 3, 14 # encoding: [0x4d,0x1a,0x4e,0x10]
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vextractuh 2, 3, 14
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# CHECK-BE: vextractuw 2, 3, 12 # encoding: [0x10,0x4c,0x1a,0x8d]
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# CHECK-LE: vextractuw 2, 3, 12 # encoding: [0x8d,0x1a,0x4c,0x10]
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vextractuw 2, 3, 12
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# CHECK-BE: vextractd 2, 3, 8 # encoding: [0x10,0x48,0x1a,0xcd]
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# CHECK-LE: vextractd 2, 3, 8 # encoding: [0xcd,0x1a,0x48,0x10]
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vextractd 2, 3, 8
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# Vector Extract Unsigned Left/Right-Indexed
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# CHECK-BE: vextublx 2, 3, 4 # encoding: [0x10,0x43,0x26,0x0d]
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# CHECK-LE: vextublx 2, 3, 4 # encoding: [0x0d,0x26,0x43,0x10]
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vextublx 2, 3, 4
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# CHECK-BE: vextubrx 2, 3, 4 # encoding: [0x10,0x43,0x27,0x0d]
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# CHECK-LE: vextubrx 2, 3, 4 # encoding: [0x0d,0x27,0x43,0x10]
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vextubrx 2, 3, 4
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# CHECK-BE: vextuhlx 2, 3, 4 # encoding: [0x10,0x43,0x26,0x4d]
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# CHECK-LE: vextuhlx 2, 3, 4 # encoding: [0x4d,0x26,0x43,0x10]
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vextuhlx 2, 3, 4
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# CHECK-BE: vextuhrx 2, 3, 4 # encoding: [0x10,0x43,0x27,0x4d]
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# CHECK-LE: vextuhrx 2, 3, 4 # encoding: [0x4d,0x27,0x43,0x10]
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vextuhrx 2, 3, 4
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# CHECK-BE: vextuwlx 2, 3, 4 # encoding: [0x10,0x43,0x26,0x8d]
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# CHECK-LE: vextuwlx 2, 3, 4 # encoding: [0x8d,0x26,0x43,0x10]
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vextuwlx 2, 3, 4
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# CHECK-BE: vextuwrx 2, 3, 4 # encoding: [0x10,0x43,0x27,0x8d]
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# CHECK-LE: vextuwrx 2, 3, 4 # encoding: [0x8d,0x27,0x43,0x10]
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vextuwrx 2, 3, 4
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# Vector Insert Element
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# CHECK-BE: vinsertb 2, 3, 15 # encoding: [0x10,0x4f,0x1b,0x0d]
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# CHECK-LE: vinsertb 2, 3, 15 # encoding: [0x0d,0x1b,0x4f,0x10]
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vinsertb 2, 3, 15
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# CHECK-BE: vinserth 2, 3, 14 # encoding: [0x10,0x4e,0x1b,0x4d]
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# CHECK-LE: vinserth 2, 3, 14 # encoding: [0x4d,0x1b,0x4e,0x10]
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vinserth 2, 3, 14
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# CHECK-BE: vinsertw 2, 3, 12 # encoding: [0x10,0x4c,0x1b,0x8d]
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# CHECK-LE: vinsertw 2, 3, 12 # encoding: [0x8d,0x1b,0x4c,0x10]
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vinsertw 2, 3, 12
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# CHECK-BE: vinsertd 2, 3, 8 # encoding: [0x10,0x48,0x1b,0xcd]
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# CHECK-LE: vinsertd 2, 3, 8 # encoding: [0xcd,0x1b,0x48,0x10]
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vinsertd 2, 3, 8
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