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[AArch32] Add patterns for VCVT{A,N,P,M}. 

Patterns for lowering libm calls to VCVT{A,N,P,M} are also included.
Phabricator Revision: http://reviews.llvm.org/D5033

llvm-svn: 216388
This commit is contained in:
Chad Rosier 2014-08-25 16:56:33 +00:00
parent dc8caada51
commit e62f365458
2 changed files with 130 additions and 9 deletions
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22
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -627,27 +627,30 @@ def : Pat<(f16_to_fp GPR:$a),
def : Pat<(f64 (f16_to_fp GPR:$a)),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
multiclass vcvt_inst<string opc, bits<2> rm> {
multiclass vcvt_inst<string opc, bits<2> rm,
SDPatternOperator node = null_frag> {
let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vcvt", opc, ".s32.f32\t$Sd, $Sm"),
[]>, Requires<[HasFPARMv8]> {
[(set SPR:$Sd, (arm_ftosi (node SPR:$Sm)))]>,
Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
(outs SPR:$Sd), (ins SPR:$Sm),
NoItinerary, !strconcat("vcvt", opc, ".u32.f32\t$Sd, $Sm"),
[]>, Requires<[HasFPARMv8]> {
[(set SPR:$Sd, (arm_ftoui (node SPR:$Sm)))]>,
Requires<[HasFPARMv8]> {
let Inst{17-16} = rm;
}
def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, !strconcat("vcvt", opc, ".s32.f64\t$Sd, $Dm"),
[]>, Requires<[HasFPARMv8, HasDPVFP]> {
[(set SPR:$Sd, (arm_ftosi (f64 (node (f64 DPR:$Dm)))))]>,
Requires<[HasFPARMv8, HasDPVFP]> {
bits<5> Dm;
let Inst{17-16} = rm;
@ -661,7 +664,8 @@ multiclass vcvt_inst<string opc, bits<2> rm> {
def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
(outs SPR:$Sd), (ins DPR:$Dm),
NoItinerary, !strconcat("vcvt", opc, ".u32.f64\t$Sd, $Dm"),
[]>, Requires<[HasFPARMv8, HasDPVFP]> {
[(set SPR:$Sd, (arm_ftoui (f64 (node (f64 DPR:$Dm)))))]>,
Requires<[HasFPARMv8, HasDPVFP]> {
bits<5> Dm;
let Inst{17-16} = rm;
@ -674,10 +678,10 @@ multiclass vcvt_inst<string opc, bits<2> rm> {
}
}
defm VCVTA : vcvt_inst<"a", 0b00>;
defm VCVTA : vcvt_inst<"a", 0b00, frnd>;
defm VCVTN : vcvt_inst<"n", 0b01>;
defm VCVTP : vcvt_inst<"p", 0b10>;
defm VCVTM : vcvt_inst<"m", 0b11>;
defm VCVTP : vcvt_inst<"p", 0b10, fceil>;
defm VCVTM : vcvt_inst<"m", 0b11, ffloor>;
def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0,
(outs DPR:$Dd), (ins DPR:$Dm),

117
llvm/test/CodeGen/ARM/arm32-round-conv.ll Normal file
View File

@ -0,0 +1,117 @@
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+fp-armv8 | FileCheck %s
; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 | FileCheck %s
; CHECK-LABEL: test1
; CHECK: vcvtm.s32.f32
define i32 @test1(float %a) {
entry:
%call = call float @floorf(float %a) nounwind readnone
%conv = fptosi float %call to i32
ret i32 %conv
}
; CHECK-LABEL: test2
; CHECK: vcvtm.u32.f32
define i32 @test2(float %a) {
entry:
%call = call float @floorf(float %a) nounwind readnone
%conv = fptoui float %call to i32
ret i32 %conv
}
; CHECK-LABEL: test3
; CHECK: vcvtm.s32.f64
define i32 @test3(double %a) {
entry:
%call = call double @floor(double %a) nounwind readnone
%conv = fptosi double %call to i32
ret i32 %conv
}
; CHECK-LABEL: test4
; CHECK: vcvtm.u32.f64
define i32 @test4(double %a) {
entry:
%call = call double @floor(double %a) nounwind readnone
%conv = fptoui double %call to i32
ret i32 %conv
}
; CHECK-LABEL: test5
; CHECK: vcvtp.s32.f32
define i32 @test5(float %a) {
entry:
%call = call float @ceilf(float %a) nounwind readnone
%conv = fptosi float %call to i32
ret i32 %conv
}
; CHECK-LABEL: test6
; CHECK: vcvtp.u32.f32
define i32 @test6(float %a) {
entry:
%call = call float @ceilf(float %a) nounwind readnone
%conv = fptoui float %call to i32
ret i32 %conv
}
; CHECK-LABEL: test7
; CHECK: vcvtp.s32.f64
define i32 @test7(double %a) {
entry:
%call = call double @ceil(double %a) nounwind readnone
%conv = fptosi double %call to i32
ret i32 %conv
}
; CHECK-LABEL: test8
; CHECK: vcvtp.u32.f64
define i32 @test8(double %a) {
entry:
%call = call double @ceil(double %a) nounwind readnone
%conv = fptoui double %call to i32
ret i32 %conv
}
; CHECK-LABEL: test9
; CHECK: vcvta.s32.f32
define i32 @test9(float %a) {
entry:
%call = call float @roundf(float %a) nounwind readnone
%conv = fptosi float %call to i32
ret i32 %conv
}
; CHECK-LABEL: test10
; CHECK: vcvta.u32.f32
define i32 @test10(float %a) {
entry:
%call = call float @roundf(float %a) nounwind readnone
%conv = fptoui float %call to i32
ret i32 %conv
}
; CHECK-LABEL: test11
; CHECK: vcvta.s32.f64
define i32 @test11(double %a) {
entry:
%call = call double @round(double %a) nounwind readnone
%conv = fptosi double %call to i32
ret i32 %conv
}
; CHECK-LABEL: test12
; CHECK: vcvta.u32.f64
define i32 @test12(double %a) {
entry:
%call = call double @round(double %a) nounwind readnone
%conv = fptoui double %call to i32
ret i32 %conv
}
declare float @floorf(float) nounwind readnone
declare double @floor(double) nounwind readnone
declare float @ceilf(float) nounwind readnone
declare double @ceil(double) nounwind readnone
declare float @roundf(float) nounwind readnone
declare double @round(double) nounwind readnone