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Add a MachineOperand::isTied() flag. 

While in SSA form, a MachineInstr can have pairs of tied defs and uses.
The tied operands are used to represent read-modify-write operands that
must be assigned the same physical register.

Previously, tied operand pairs were computed from fixed MCInstrDesc
fields, or by using black magic on inline assembly instructions.

The isTied flag makes it possible to add tied operands to any
instruction while getting rid of (some of) the inlineasm magic.

Tied operands on normal instructions are needed to represent predicated
individual instructions in SSA form. An extra <tied,imp-use> operand is
required to represent the output value when the instruction predicate is
false.

Adding a predicate to:

  %vreg0<def> = ADD %vreg1, %vreg2

Will look like:

  %vreg0<tied,def> = ADD %vreg1, %vreg2, pred:3, %vreg7<tied,imp-use>

The virtual register %vreg7 is the value given to %vreg0 when the
predicate is false. It will be assigned the same physreg as %vreg0.

This commit adds the isTied flag and sets it based on MCInstrDesc when
building an instruction. The flag is not used for anything yet.

llvm-svn: 162774
This commit is contained in:
Jakob Stoklund Olesen 2012-08-28 18:34:41 +00:00
parent f70b7e284c
commit e56c60c5eb
2 changed files with 53 additions and 21 deletions
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19
llvm/include/llvm/CodeGen/MachineOperand.h
View File

@ -124,6 +124,14 @@ private:
/// model the GCC inline asm '&' constraint modifier.
bool IsEarlyClobber : 1;
/// IsTied - True if this MO_Register operand is tied to another operand on
/// the instruction. Tied operands form def-use pairs that must be assigned
/// the same physical register by the register allocator, but they will have
/// different virtual registers while the code is in SSA form.
///
/// See MachineInstr::isRegTiedToUseOperand() and isRegTiedToDefOperand().
bool IsTied : 1;
/// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo,
/// not a real instruction. Such uses should be ignored during codegen.
bool IsDebug : 1;
@ -299,6 +307,11 @@ public:
return IsEarlyClobber;
}
bool isTied() const {
assert(isReg() && "Wrong MachineOperand accessor");
return IsTied;
}
bool isDebug() const {
assert(isReg() && "Wrong MachineOperand accessor");
return IsDebug;
@ -377,6 +390,11 @@ public:
IsEarlyClobber = Val;
}
void setIsTied(bool Val = true) {
assert(isReg() && "Wrong MachineOperand accessor");
IsTied = Val;
}
void setIsDebug(bool Val = true) {
assert(isReg() && IsDef && "Wrong MachineOperand accessor");
IsDebug = Val;
@ -559,6 +577,7 @@ public:
Op.IsUndef = isUndef;
Op.IsInternalRead = isInternalRead;
Op.IsEarlyClobber = isEarlyClobber;
Op.IsTied = false;
Op.IsDebug = isDebug;
Op.SmallContents.RegNo = Reg;
Op.Contents.Reg.Prev = 0;

55
llvm/lib/CodeGen/MachineInstr.cpp
View File

@ -262,7 +262,7 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
OS << PrintReg(getReg(), TRI, getSubReg());
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isInternalRead() || isEarlyClobber()) {
isInternalRead() || isEarlyClobber() || isTied()) {
OS << '<';
bool NeedComma = false;
if (isDef()) {
@ -282,27 +282,30 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
NeedComma = true;
}
if (isKill() || isDead() || (isUndef() && isUse()) || isInternalRead()) {
if (isKill()) {
if (NeedComma) OS << ',';
NeedComma = false;
if (isKill()) {
OS << "kill";
NeedComma = true;
}
if (isDead()) {
OS << "dead";
NeedComma = true;
}
if (isUndef() && isUse()) {
if (NeedComma) OS << ',';
OS << "undef";
NeedComma = true;
}
if (isInternalRead()) {
if (NeedComma) OS << ',';
OS << "internal";
NeedComma = true;
}
OS << "kill";
NeedComma = true;
}
if (isDead()) {
if (NeedComma) OS << ',';
OS << "dead";
NeedComma = true;
}
if (isUndef() && isUse()) {
if (NeedComma) OS << ',';
OS << "undef";
NeedComma = true;
}
if (isInternalRead()) {
if (NeedComma) OS << ',';
OS << "internal";
NeedComma = true;
}
if (isTied()) {
if (NeedComma) OS << ',';
OS << "tied";
NeedComma = true;
}
OS << '>';
}
@ -711,6 +714,16 @@ void MachineInstr::addOperand(const MachineOperand &Op) {
// Add the new operand to RegInfo.
if (RegInfo)
RegInfo->addRegOperandToUseList(&Operands[OpNo]);
// Set the IsTied bit if MC indicates this use is tied to a def.
if (Operands[OpNo].isUse()) {
int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
if (DefIdx != -1) {
MachineOperand &DefMO = getOperand(DefIdx);
assert(DefMO.isDef() && "Use tied to operand that isn't a def");
DefMO.IsTied = true;
Operands[OpNo].IsTied = true;
}
}
// If the register operand is flagged as early, mark the operand as such.
if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
Operands[OpNo].setIsEarlyClobber(true);