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Revert "StructurizeCFG: Test for branch divergence correctly" 

This reverts commit r325881.

Breaks many bots

llvm-svn: 326037
This commit is contained in:
Adam Nemet 2018-02-24 17:29:09 +00:00
parent 38bbc16a8b
commit e4e1de60aa
4 changed files with 6 additions and 103 deletions
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8
llvm/include/llvm/Analysis/DivergenceAnalysis.h
View File

@ -35,16 +35,10 @@ public:
// Print all divergent branches in the function.
void print(raw_ostream &OS, const Module *) const override;
// Returns true if V is divergent at its definition.
//
// Even if this function returns false, V may still be divergent when used
// in a different basic block.
// Returns true if V is divergent.
bool isDivergent(const Value *V) const { return DivergentValues.count(V); }
// Returns true if V is uniform/non-divergent.
//
// Even if this function returns true, V may still be divergent when used
// in a different basic block.
bool isUniform(const Value *V) const { return !isDivergent(V); }
private:

15
llvm/lib/Transforms/Scalar/StructurizeCFG.cpp
View File

@ -55,12 +55,6 @@ static const char *const FlowBlockName = "Flow";
namespace {
static cl::opt<bool> ForceSkipUniformRegions(
"structurizecfg-skip-uniform-regions",
cl::Hidden,
cl::desc("Force whether the StructurizeCFG pass skips uniform regions"),
cl::init(false));
// Definition of the complex types used in this pass.
using BBValuePair = std::pair<BasicBlock *, Value *>;
@ -248,11 +242,8 @@ class StructurizeCFG : public RegionPass {
public:
static char ID;
explicit StructurizeCFG(bool SkipUniformRegions_ = false)
: RegionPass(ID),
SkipUniformRegions(SkipUniformRegions_) {
if (ForceSkipUniformRegions.getNumOccurrences())
SkipUniformRegions = ForceSkipUniformRegions.getValue();
explicit StructurizeCFG(bool SkipUniformRegions = false)
: RegionPass(ID), SkipUniformRegions(SkipUniformRegions) {
initializeStructurizeCFGPass(*PassRegistry::getPassRegistry());
}
@ -894,7 +885,7 @@ static bool hasOnlyUniformBranches(const Region *R,
if (!Br || !Br->isConditional())
continue;
if (!DA.isUniform(Br))
if (!DA.isUniform(Br->getCondition()))
return false;
DEBUG(dbgs() << "BB: " << BB->getName() << " has uniform terminator\n");
}

4
llvm/test/CodeGen/AMDGPU/control-flow-optnone.ll
View File

@ -15,8 +15,8 @@
; GCN: s_mov_b64 exec
; GCN: s_or_b64 exec, exec
; GCN: s_cmp_eq_u32
; GCN: s_cbranch_scc1
; GCN: v_cmp_eq_u32
; GCN: s_cbranch_vccnz
; GCN-NEXT: s_branch
define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
bb:

82
llvm/test/Transforms/StructurizeCFG/AMDGPU/uniform-regions.ll
View File

@ -1,82 +0,0 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=amdgcn-- -S -o - -structurizecfg -structurizecfg-skip-uniform-regions < %s | FileCheck %s
define amdgpu_cs void @uniform(i32 inreg %v) {
; CHECK-LABEL: @uniform(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CC:%.*]] = icmp eq i32 [[V:%.*]], 0
; CHECK-NEXT: br i1 [[CC]], label [[IF:%.*]], label [[END:%.*]], !structurizecfg.uniform !0
; CHECK: if:
; CHECK-NEXT: br label [[END]], !structurizecfg.uniform !0
; CHECK: end:
; CHECK-NEXT: ret void
;
entry:
%cc = icmp eq i32 %v, 0
br i1 %cc, label %if, label %end
if:
br label %end
end:
ret void
}
define amdgpu_cs void @nonuniform(i32 addrspace(2)* %ptr) {
; CHECK-LABEL: @nonuniform(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
; CHECK: for.body:
; CHECK-NEXT: [[I:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP0:%.*]], [[FLOW:%.*]] ]
; CHECK-NEXT: [[CC:%.*]] = icmp ult i32 [[I]], 4
; CHECK-NEXT: br i1 [[CC]], label [[MID_LOOP:%.*]], label [[FLOW]]
; CHECK: mid.loop:
; CHECK-NEXT: [[V:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
; CHECK-NEXT: [[CC2:%.*]] = icmp eq i32 [[V]], 0
; CHECK-NEXT: br i1 [[CC2]], label [[END_LOOP:%.*]], label [[FLOW1:%.*]]
; CHECK: Flow:
; CHECK-NEXT: [[TMP0]] = phi i32 [ [[TMP2:%.*]], [[FLOW1]] ], [ undef, [[FOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = phi i1 [ [[TMP3:%.*]], [[FLOW1]] ], [ true, [[FOR_BODY]] ]
; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_END:%.*]], label [[FOR_BODY]]
; CHECK: end.loop:
; CHECK-NEXT: [[I_INC:%.*]] = add i32 [[I]], 1
; CHECK-NEXT: br label [[FLOW1]]
; CHECK: Flow1:
; CHECK-NEXT: [[TMP2]] = phi i32 [ [[I_INC]], [[END_LOOP]] ], [ undef, [[MID_LOOP]] ]
; CHECK-NEXT: [[TMP3]] = phi i1 [ false, [[END_LOOP]] ], [ true, [[MID_LOOP]] ]
; CHECK-NEXT: br label [[FLOW]]
; CHECK: for.end:
; CHECK-NEXT: br i1 [[CC]], label [[IF:%.*]], label [[END:%.*]]
; CHECK: if:
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: ret void
;
entry:
br label %for.body
for.body:
%i = phi i32 [0, %entry], [%i.inc, %end.loop]
%cc = icmp ult i32 %i, 4
br i1 %cc, label %mid.loop, label %for.end
mid.loop:
%v = call i32 @llvm.amdgcn.workitem.id.x()
%cc2 = icmp eq i32 %v, 0
br i1 %cc2, label %end.loop, label %for.end
end.loop:
%i.inc = add i32 %i, 1
br label %for.body
for.end:
br i1 %cc, label %if, label %end
if:
br label %end
end:
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()