Temporarily revert "Update branch coalescing to be a PowerPC specific pass"
From comments and code review it wasn't intended to be enabled by default yet. This reverts commit r311588. llvm-svn: 312214
This commit is contained in:
parent
376f1bd73c
commit
e42ac21499
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@ -409,6 +409,9 @@ namespace llvm {
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/// This pass frees the memory occupied by the MachineFunction.
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/// This pass frees the memory occupied by the MachineFunction.
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FunctionPass *createFreeMachineFunctionPass();
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FunctionPass *createFreeMachineFunctionPass();
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/// This pass combine basic blocks guarded by the same branch.
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extern char &BranchCoalescingID;
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/// This pass performs outlining on machine instructions directly before
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/// This pass performs outlining on machine instructions directly before
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/// printing assembly.
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/// printing assembly.
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ModulePass *createMachineOutlinerPass();
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ModulePass *createMachineOutlinerPass();
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@ -76,6 +76,7 @@ void initializeBasicAAWrapperPassPass(PassRegistry&);
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void initializeBlockExtractorPassPass(PassRegistry&);
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void initializeBlockExtractorPassPass(PassRegistry&);
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void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry&);
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void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry&);
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void initializeBoundsCheckingPass(PassRegistry&);
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void initializeBoundsCheckingPass(PassRegistry&);
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void initializeBranchCoalescingPass(PassRegistry&);
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void initializeBranchFolderPassPass(PassRegistry&);
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void initializeBranchFolderPassPass(PassRegistry&);
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void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry&);
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void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry&);
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void initializeBranchRelaxationPass(PassRegistry&);
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void initializeBranchRelaxationPass(PassRegistry&);
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@ -13,7 +13,6 @@
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///
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineDominators.h"
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@ -28,18 +27,18 @@
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using namespace llvm;
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using namespace llvm;
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#define DEBUG_TYPE "ppc-branch-coalescing"
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#define DEBUG_TYPE "branch-coalescing"
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static cl::opt<cl::boolOrDefault>
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EnableBranchCoalescing("enable-branch-coalesce", cl::Hidden,
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cl::desc("enable coalescing of duplicate branches"));
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STATISTIC(NumBlocksCoalesced, "Number of blocks coalesced");
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STATISTIC(NumBlocksCoalesced, "Number of blocks coalesced");
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STATISTIC(NumPHINotMoved, "Number of PHI Nodes that cannot be merged");
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STATISTIC(NumPHINotMoved, "Number of PHI Nodes that cannot be merged");
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STATISTIC(NumBlocksNotCoalesced, "Number of blocks not coalesced");
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STATISTIC(NumBlocksNotCoalesced, "Number of blocks not coalesced");
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namespace llvm {
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void initializePPCBranchCoalescingPass(PassRegistry&);
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// PPCBranchCoalescing
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// BranchCoalescing
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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///
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///
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/// Improve scheduling by coalescing branches that depend on the same condition.
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/// Improve scheduling by coalescing branches that depend on the same condition.
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@ -47,17 +46,13 @@ namespace llvm {
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/// and attempts to merge the blocks together. Such opportunities arise from
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/// and attempts to merge the blocks together. Such opportunities arise from
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/// the expansion of select statements in the IR.
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/// the expansion of select statements in the IR.
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///
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///
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/// This pass does not handle implicit operands on branch statements. In order
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/// For example, consider the following LLVM IR:
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/// to run on targets that use implicit operands, changes need to be made in the
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/// canCoalesceBranch and canMerge methods.
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///
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///
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/// Example: the following LLVM IR
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/// %test = icmp eq i32 %x 0
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/// %tmp1 = select i1 %test, double %a, double 2.000000e-03
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/// %tmp2 = select i1 %test, double %b, double 5.000000e-03
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///
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///
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/// %test = icmp eq i32 %x 0
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/// This IR expands to the following machine code on PowerPC:
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/// %tmp1 = select i1 %test, double %a, double 2.000000e-03
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/// %tmp2 = select i1 %test, double %b, double 5.000000e-03
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///
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/// expands to the following machine code:
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///
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///
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/// BB#0: derived from LLVM BB %entry
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/// BB#0: derived from LLVM BB %entry
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/// Live Ins: %F1 %F3 %X6
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/// Live Ins: %F1 %F3 %X6
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@ -137,7 +132,7 @@ namespace llvm {
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namespace {
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namespace {
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class PPCBranchCoalescing : public MachineFunctionPass {
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class BranchCoalescing : public MachineFunctionPass {
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struct CoalescingCandidateInfo {
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struct CoalescingCandidateInfo {
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MachineBasicBlock *BranchBlock; // Block containing the branch
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MachineBasicBlock *BranchBlock; // Block containing the branch
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MachineBasicBlock *BranchTargetBlock; // Block branched to
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MachineBasicBlock *BranchTargetBlock; // Block branched to
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@ -162,11 +157,15 @@ class PPCBranchCoalescing : public MachineFunctionPass {
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bool validateCandidates(CoalescingCandidateInfo &SourceRegion,
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bool validateCandidates(CoalescingCandidateInfo &SourceRegion,
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CoalescingCandidateInfo &TargetRegion) const;
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CoalescingCandidateInfo &TargetRegion) const;
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static bool isBranchCoalescingEnabled() {
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return EnableBranchCoalescing == cl::BOU_TRUE;
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}
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public:
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public:
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static char ID;
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static char ID;
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PPCBranchCoalescing() : MachineFunctionPass(ID) {
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BranchCoalescing() : MachineFunctionPass(ID) {
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initializePPCBranchCoalescingPass(*PassRegistry::getPassRegistry());
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initializeBranchCoalescingPass(*PassRegistry::getPassRegistry());
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}
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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@ -191,25 +190,21 @@ public:
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};
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};
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} // End anonymous namespace.
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} // End anonymous namespace.
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char PPCBranchCoalescing::ID = 0;
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char BranchCoalescing::ID = 0;
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/// createPPCBranchCoalescingPass - returns an instance of the Branch Coalescing
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char &llvm::BranchCoalescingID = BranchCoalescing::ID;
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/// Pass
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FunctionPass *llvm::createPPCBranchCoalescingPass() {
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return new PPCBranchCoalescing();
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}
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INITIALIZE_PASS_BEGIN(PPCBranchCoalescing, DEBUG_TYPE,
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INITIALIZE_PASS_BEGIN(BranchCoalescing, DEBUG_TYPE,
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"Branch Coalescing", false, false)
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"Branch Coalescing", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachinePostDominatorTree)
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INITIALIZE_PASS_END(PPCBranchCoalescing, DEBUG_TYPE, "Branch Coalescing",
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INITIALIZE_PASS_END(BranchCoalescing, DEBUG_TYPE, "Branch Coalescing",
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false, false)
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false, false)
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PPCBranchCoalescing::CoalescingCandidateInfo::CoalescingCandidateInfo()
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BranchCoalescing::CoalescingCandidateInfo::CoalescingCandidateInfo()
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: BranchBlock(nullptr), BranchTargetBlock(nullptr),
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: BranchBlock(nullptr), BranchTargetBlock(nullptr),
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FallThroughBlock(nullptr), MustMoveDown(false), MustMoveUp(false) {}
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FallThroughBlock(nullptr), MustMoveDown(false), MustMoveUp(false) {}
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void PPCBranchCoalescing::CoalescingCandidateInfo::clear() {
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void BranchCoalescing::CoalescingCandidateInfo::clear() {
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BranchBlock = nullptr;
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BranchBlock = nullptr;
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BranchTargetBlock = nullptr;
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BranchTargetBlock = nullptr;
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FallThroughBlock = nullptr;
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FallThroughBlock = nullptr;
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@ -218,7 +213,7 @@ void PPCBranchCoalescing::CoalescingCandidateInfo::clear() {
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MustMoveUp = false;
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MustMoveUp = false;
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}
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}
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void PPCBranchCoalescing::initialize(MachineFunction &MF) {
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void BranchCoalescing::initialize(MachineFunction &MF) {
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MDT = &getAnalysis<MachineDominatorTree>();
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MDT = &getAnalysis<MachineDominatorTree>();
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MPDT = &getAnalysis<MachinePostDominatorTree>();
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MPDT = &getAnalysis<MachinePostDominatorTree>();
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TII = MF.getSubtarget().getInstrInfo();
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TII = MF.getSubtarget().getInstrInfo();
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@ -235,7 +230,7 @@ void PPCBranchCoalescing::initialize(MachineFunction &MF) {
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///\param[in,out] Cand The coalescing candidate to analyze
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///\param[in,out] Cand The coalescing candidate to analyze
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///\return true if and only if the branch can be coalesced, false otherwise
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///\return true if and only if the branch can be coalesced, false otherwise
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///
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///
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bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) {
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bool BranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) {
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DEBUG(dbgs() << "Determine if branch block " << Cand.BranchBlock->getNumber()
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DEBUG(dbgs() << "Determine if branch block " << Cand.BranchBlock->getNumber()
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<< " can be coalesced:");
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<< " can be coalesced:");
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MachineBasicBlock *FalseMBB = nullptr;
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MachineBasicBlock *FalseMBB = nullptr;
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@ -251,19 +246,6 @@ bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) {
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if (!I.isBranch())
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if (!I.isBranch())
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continue;
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continue;
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// The analyzeBranch method does not include any implicit operands.
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// This is not an issue on PPC but must be handled on other targets.
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// For this pass to be made target-independent, the analyzeBranch API
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// need to be updated to support implicit operands and there would
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// need to be a way to verify that any implicit operands would not be
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// clobbered by merging blocks. This would include identifying the
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// implicit operands as well as the basic block they are defined in.
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// This could be done by changing the analyzeBranch API to have it also
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// record and return the implicit operands and the blocks where they are
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// defined. Alternatively, the BranchCoalescing code would need to be
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// extended to identify the implicit operands. The analysis in canMerge
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// must then be extended to prove that none of the implicit operands are
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// changed in the blocks that are combined during coalescing.
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if (I.getNumOperands() != I.getNumExplicitOperands()) {
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if (I.getNumOperands() != I.getNumExplicitOperands()) {
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DEBUG(dbgs() << "Terminator contains implicit operands - skip : " << I
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DEBUG(dbgs() << "Terminator contains implicit operands - skip : " << I
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<< "\n");
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<< "\n");
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@ -327,7 +309,7 @@ bool PPCBranchCoalescing::canCoalesceBranch(CoalescingCandidateInfo &Cand) {
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/// \param[in] OpList2 operand list
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/// \param[in] OpList2 operand list
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/// \return true if and only if the operands lists are identical
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/// \return true if and only if the operands lists are identical
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///
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///
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bool PPCBranchCoalescing::identicalOperands(
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bool BranchCoalescing::identicalOperands(
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ArrayRef<MachineOperand> OpList1, ArrayRef<MachineOperand> OpList2) const {
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ArrayRef<MachineOperand> OpList1, ArrayRef<MachineOperand> OpList2) const {
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if (OpList1.size() != OpList2.size()) {
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if (OpList1.size() != OpList2.size()) {
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@ -379,7 +361,7 @@ bool PPCBranchCoalescing::identicalOperands(
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/// \param[in] SourceMBB block to move PHI instructions from
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/// \param[in] SourceMBB block to move PHI instructions from
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/// \param[in] TargetMBB block to move PHI instructions to
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/// \param[in] TargetMBB block to move PHI instructions to
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///
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///
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void PPCBranchCoalescing::moveAndUpdatePHIs(MachineBasicBlock *SourceMBB,
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void BranchCoalescing::moveAndUpdatePHIs(MachineBasicBlock *SourceMBB,
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MachineBasicBlock *TargetMBB) {
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MachineBasicBlock *TargetMBB) {
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MachineBasicBlock::iterator MI = SourceMBB->begin();
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MachineBasicBlock::iterator MI = SourceMBB->begin();
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@ -412,7 +394,7 @@ void PPCBranchCoalescing::moveAndUpdatePHIs(MachineBasicBlock *SourceMBB,
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/// \return true if it is safe to move MI to beginning of TargetMBB,
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/// \return true if it is safe to move MI to beginning of TargetMBB,
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/// false otherwise.
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/// false otherwise.
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///
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///
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bool PPCBranchCoalescing::canMoveToBeginning(const MachineInstr &MI,
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bool BranchCoalescing::canMoveToBeginning(const MachineInstr &MI,
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const MachineBasicBlock &TargetMBB
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const MachineBasicBlock &TargetMBB
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) const {
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) const {
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@ -443,7 +425,7 @@ bool PPCBranchCoalescing::canMoveToBeginning(const MachineInstr &MI,
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/// \return true if it is safe to move MI to end of TargetMBB,
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/// \return true if it is safe to move MI to end of TargetMBB,
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/// false otherwise.
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/// false otherwise.
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///
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///
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bool PPCBranchCoalescing::canMoveToEnd(const MachineInstr &MI,
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bool BranchCoalescing::canMoveToEnd(const MachineInstr &MI,
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const MachineBasicBlock &TargetMBB
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const MachineBasicBlock &TargetMBB
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) const {
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) const {
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@ -475,7 +457,7 @@ bool PPCBranchCoalescing::canMoveToEnd(const MachineInstr &MI,
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/// \return true if all instructions in SourceRegion.BranchBlock can be merged
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/// \return true if all instructions in SourceRegion.BranchBlock can be merged
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/// into a block in TargetRegion; false otherwise.
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/// into a block in TargetRegion; false otherwise.
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///
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///
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bool PPCBranchCoalescing::validateCandidates(
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bool BranchCoalescing::validateCandidates(
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CoalescingCandidateInfo &SourceRegion,
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CoalescingCandidateInfo &SourceRegion,
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CoalescingCandidateInfo &TargetRegion) const {
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CoalescingCandidateInfo &TargetRegion) const {
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@ -518,7 +500,7 @@ bool PPCBranchCoalescing::validateCandidates(
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/// \return true if all instructions in SourceRegion.BranchBlock can be merged
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/// \return true if all instructions in SourceRegion.BranchBlock can be merged
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/// into a block in TargetRegion, false otherwise.
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/// into a block in TargetRegion, false otherwise.
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///
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///
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bool PPCBranchCoalescing::canMerge(CoalescingCandidateInfo &SourceRegion,
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bool BranchCoalescing::canMerge(CoalescingCandidateInfo &SourceRegion,
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CoalescingCandidateInfo &TargetRegion) const {
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CoalescingCandidateInfo &TargetRegion) const {
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if (!validateCandidates(SourceRegion, TargetRegion))
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if (!validateCandidates(SourceRegion, TargetRegion))
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return false;
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return false;
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@ -623,7 +605,7 @@ bool PPCBranchCoalescing::canMerge(CoalescingCandidateInfo &SourceRegion,
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/// \param[in] SourceRegion The candidate to move blocks from
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/// \param[in] SourceRegion The candidate to move blocks from
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/// \param[in] TargetRegion The candidate to move blocks to
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/// \param[in] TargetRegion The candidate to move blocks to
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///
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///
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bool PPCBranchCoalescing::mergeCandidates(CoalescingCandidateInfo &SourceRegion,
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bool BranchCoalescing::mergeCandidates(CoalescingCandidateInfo &SourceRegion,
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CoalescingCandidateInfo &TargetRegion) {
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CoalescingCandidateInfo &TargetRegion) {
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if (SourceRegion.MustMoveUp && SourceRegion.MustMoveDown) {
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if (SourceRegion.MustMoveUp && SourceRegion.MustMoveDown) {
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@ -703,9 +685,10 @@ bool PPCBranchCoalescing::mergeCandidates(CoalescingCandidateInfo &SourceRegion,
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return true;
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return true;
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}
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}
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bool PPCBranchCoalescing::runOnMachineFunction(MachineFunction &MF) {
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bool BranchCoalescing::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(*MF.getFunction()) || MF.empty())
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if (skipFunction(*MF.getFunction()) || MF.empty() ||
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!isBranchCoalescingEnabled())
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return false;
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return false;
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bool didSomething = false;
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bool didSomething = false;
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@ -4,6 +4,7 @@ add_llvm_library(LLVMCodeGen
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Analysis.cpp
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Analysis.cpp
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AtomicExpandPass.cpp
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AtomicExpandPass.cpp
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BasicTargetTransformInfo.cpp
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BasicTargetTransformInfo.cpp
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BranchCoalescing.cpp
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BranchFolding.cpp
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BranchFolding.cpp
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BranchRelaxation.cpp
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BranchRelaxation.cpp
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BuiltinGCs.cpp
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BuiltinGCs.cpp
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@ -21,6 +21,7 @@ using namespace llvm;
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/// initializeCodeGen - Initialize all passes linked into the CodeGen library.
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/// initializeCodeGen - Initialize all passes linked into the CodeGen library.
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void llvm::initializeCodeGen(PassRegistry &Registry) {
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void llvm::initializeCodeGen(PassRegistry &Registry) {
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initializeAtomicExpandPass(Registry);
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initializeAtomicExpandPass(Registry);
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initializeBranchCoalescingPass(Registry);
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initializeBranchFolderPassPass(Registry);
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initializeBranchFolderPassPass(Registry);
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initializeBranchRelaxationPass(Registry);
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initializeBranchRelaxationPass(Registry);
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initializeCodeGenPreparePass(Registry);
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initializeCodeGenPreparePass(Registry);
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@ -919,6 +919,9 @@ void TargetPassConfig::addMachineSSAOptimization() {
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addPass(&MachineLICMID, false);
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addPass(&MachineLICMID, false);
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addPass(&MachineCSEID, false);
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addPass(&MachineCSEID, false);
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// Coalesce basic blocks with the same branch condition
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addPass(&BranchCoalescingID);
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addPass(&MachineSinkingID);
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addPass(&MachineSinkingID);
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addPass(&PeepholeOptimizerID);
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addPass(&PeepholeOptimizerID);
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@ -16,7 +16,6 @@ add_llvm_target(PowerPCCodeGen
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PPCBoolRetToInt.cpp
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PPCBoolRetToInt.cpp
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PPCAsmPrinter.cpp
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PPCAsmPrinter.cpp
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PPCBranchSelector.cpp
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PPCBranchSelector.cpp
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PPCBranchCoalescing.cpp
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PPCCCState.cpp
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PPCCCState.cpp
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PPCCTRLoops.cpp
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PPCCTRLoops.cpp
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PPCHazardRecognizers.cpp
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PPCHazardRecognizers.cpp
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@ -41,7 +41,6 @@ namespace llvm {
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FunctionPass *createPPCVSXSwapRemovalPass();
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FunctionPass *createPPCVSXSwapRemovalPass();
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FunctionPass *createPPCMIPeepholePass();
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FunctionPass *createPPCMIPeepholePass();
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FunctionPass *createPPCBranchSelectionPass();
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FunctionPass *createPPCBranchSelectionPass();
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||||||
FunctionPass *createPPCBranchCoalescingPass();
|
|
||||||
FunctionPass *createPPCQPXLoadSplatPass();
|
FunctionPass *createPPCQPXLoadSplatPass();
|
||||||
FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
|
FunctionPass *createPPCISelDag(PPCTargetMachine &TM, CodeGenOpt::Level OL);
|
||||||
FunctionPass *createPPCTLSDynamicCallPass();
|
FunctionPass *createPPCTLSDynamicCallPass();
|
||||||
|
|
|
@ -40,10 +40,6 @@
|
||||||
|
|
||||||
using namespace llvm;
|
using namespace llvm;
|
||||||
|
|
||||||
|
|
||||||
static cl::opt<bool>
|
|
||||||
DisableBranchCoalescing("disable-ppc-branch-coalesce", cl::Hidden,
|
|
||||||
cl::desc("disable coalescing of duplicate branches for PPC"));
|
|
||||||
static cl::
|
static cl::
|
||||||
opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
|
opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
|
||||||
cl::desc("Disable CTR loops for PPC"));
|
cl::desc("Disable CTR loops for PPC"));
|
||||||
|
@ -382,10 +378,6 @@ bool PPCPassConfig::addInstSelector() {
|
||||||
}
|
}
|
||||||
|
|
||||||
void PPCPassConfig::addMachineSSAOptimization() {
|
void PPCPassConfig::addMachineSSAOptimization() {
|
||||||
// PPCBranchCoalescingPass need to be done before machine sinking
|
|
||||||
// since it merges empty blocks.
|
|
||||||
if (!DisableBranchCoalescing && getOptLevel() != CodeGenOpt::None)
|
|
||||||
addPass(createPPCBranchCoalescingPass());
|
|
||||||
TargetPassConfig::addMachineSSAOptimization();
|
TargetPassConfig::addMachineSSAOptimization();
|
||||||
// For little endian, remove where possible the vector swap instructions
|
// For little endian, remove where possible the vector swap instructions
|
||||||
// introduced at code generation to normalize vector element order.
|
// introduced at code generation to normalize vector element order.
|
||||||
|
|
|
@ -1,10 +1,17 @@
|
||||||
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
|
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-branch-coalesce=true < %s | FileCheck %s
|
||||||
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck %s
|
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-branch-coalesce=true < %s | FileCheck %s
|
||||||
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -disable-ppc-branch-coalesce < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
|
|
||||||
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -disable-ppc-branch-coalesce < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
|
|
||||||
|
|
||||||
; Function Attrs: nounwind
|
; Function Attrs: nounwind
|
||||||
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
|
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
|
||||||
|
entry:
|
||||||
|
%test = icmp eq i32 %x, 0
|
||||||
|
%tmp1 = select i1 %test, double %a, double 2.000000e-03
|
||||||
|
%tmp2 = select i1 %test, double %b, double 0.000000e+00
|
||||||
|
%tmp3 = select i1 %test, double %c, double 5.000000e-03
|
||||||
|
|
||||||
|
%res1 = fadd double %tmp1, %tmp2
|
||||||
|
%result = fadd double %res1, %tmp3
|
||||||
|
ret double %result
|
||||||
|
|
||||||
; CHECK-LABEL: @testBranchCoal
|
; CHECK-LABEL: @testBranchCoal
|
||||||
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
|
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
|
||||||
|
@ -21,40 +28,4 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
|
||||||
; CHECK: xsadddp 0, 1, 2
|
; CHECK: xsadddp 0, 1, 2
|
||||||
; CHECK: xsadddp 1, 0, 3
|
; CHECK: xsadddp 1, 0, 3
|
||||||
; CHECK: blr
|
; CHECK: blr
|
||||||
|
|
||||||
; CHECK-NOCOALESCE-LABEL: testBranchCoal:
|
|
||||||
; CHECK-NOCOALESCE: # BB#0: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
|
|
||||||
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
|
|
||||||
; CHECK-NOCOALESCE-NEXT: # BB#1: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6
|
|
||||||
; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4
|
|
||||||
; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
|
|
||||||
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_1@toc@l
|
|
||||||
; CHECK-NOCOALESCE-NEXT: lxsdx 3, 0, 3
|
|
||||||
; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2
|
|
||||||
; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3
|
|
||||||
; CHECK-NOCOALESCE-NEXT: blr
|
|
||||||
; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
|
|
||||||
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_0@toc@l
|
|
||||||
; CHECK-NOCOALESCE-NEXT: lxsdx 1, 0, 3
|
|
||||||
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2
|
|
||||||
; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry
|
|
||||||
; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2
|
|
||||||
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3
|
|
||||||
; CHECK-NOCOALESCE-NEXT: b .LBB0_4
|
|
||||||
entry:
|
|
||||||
|
|
||||||
%test = icmp eq i32 %x, 0
|
|
||||||
%tmp1 = select i1 %test, double %a, double 2.000000e-03
|
|
||||||
%tmp2 = select i1 %test, double %b, double 0.000000e+00
|
|
||||||
%tmp3 = select i1 %test, double %c, double 5.000000e-03
|
|
||||||
|
|
||||||
%res1 = fadd double %tmp1, %tmp2
|
|
||||||
%result = fadd double %res1, %tmp3
|
|
||||||
ret double %result
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -1026,6 +1026,10 @@ entry:
|
||||||
%cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2
|
%cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2
|
||||||
ret ppc_fp128 %cond
|
ret ppc_fp128 %cond
|
||||||
|
|
||||||
|
; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion
|
||||||
|
; works, we end up with two blocks with the same predicate. These could be
|
||||||
|
; combined.
|
||||||
|
|
||||||
; CHECK-LABEL: @testppc_fp128eq
|
; CHECK-LABEL: @testppc_fp128eq
|
||||||
; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
|
; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
|
||||||
; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
|
; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
|
||||||
|
@ -1036,8 +1040,10 @@ entry:
|
||||||
; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||||
; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
|
; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
|
||||||
; CHECK: fmr 11, 9
|
; CHECK: fmr 11, 9
|
||||||
; CHECK: fmr 12, 10
|
|
||||||
; CHECK: .LBB[[BB1]]:
|
; CHECK: .LBB[[BB1]]:
|
||||||
|
; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
|
||||||
|
; CHECK: fmr 12, 10
|
||||||
|
; CHECK: .LBB[[BB2]]:
|
||||||
; CHECK-DAG: fmr 1, 11
|
; CHECK-DAG: fmr 1, 11
|
||||||
; CHECK-DAG: fmr 2, 12
|
; CHECK-DAG: fmr 2, 12
|
||||||
; CHECK: blr
|
; CHECK: blr
|
||||||
|
|
Loading…
Reference in New Issue