From e379107cdcbe5fc829db809747fa02d441f3a35d Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Tue, 23 Jun 2009 18:14:38 +0000
Subject: [PATCH] Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.

llvm-svn: 73975
---
 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 12 ++++++------
 llvm/lib/Target/ARM/ARMInstrThumb2.td   |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
index ee9dadff151b..be543a91ef26 100644
--- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -92,8 +92,8 @@ public:
   bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
                              SDValue &OffImm);
 
-  bool SelectShifterOperand(SDValue Op, SDValue N,
-                            SDValue &BaseReg, SDValue &Opc);
+  bool SelectThumb2ShifterOperandReg(SDValue Op, SDValue N,
+                                     SDValue &BaseReg, SDValue &Opc);
 
   bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
                                SDValue &B, SDValue &C);
@@ -520,10 +520,10 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
   return false;
 }
 
-bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op,
-                                           SDValue N,
-                                           SDValue &BaseReg,
-                                           SDValue &Opc) {
+bool ARMDAGToDAGISel::SelectThumb2ShifterOperandReg(SDValue Op,
+                                                    SDValue N,
+                                                    SDValue &BaseReg,
+                                                    SDValue &Opc) {
   ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
 
   // Don't match base register only case. That is matched to a separate
diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 9790c2bdee6f..e0617e466208 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -14,7 +14,7 @@
 // Shifted operands. No register controlled shifts for Thumb2.
 // Note: We do not support rrx shifted operands yet.
 def t2_so_reg : Operand<i32>,    // reg imm
-                ComplexPattern<i32, 2, "SelectShifterOperand",
+                ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg",
                                [shl,srl,sra,rotr]> {
   let PrintMethod = "printSOOperand";
   let MIOperandInfo = (ops GPR, i32imm);