Revert r130178. It turned out to be not the optimal path to emit complex location expressions.
llvm-svn: 130326
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f6c61a34bf
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@ -384,8 +384,7 @@ namespace llvm {
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virtual unsigned getISAEncoding() { return 0; }
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virtual unsigned getISAEncoding() { return 0; }
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/// EmitDwarfRegOp - Emit dwarf register operation.
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/// EmitDwarfRegOp - Emit dwarf register operation.
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virtual void EmitDwarfRegOp(const MachineLocation &MLoc,
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virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
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unsigned ExtraExprSize = 0) const;
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//===------------------------------------------------------------------===//
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//===------------------------------------------------------------------===//
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// Dwarf Lowering Routines
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// Dwarf Lowering Routines
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@ -750,8 +750,7 @@ getDebugValueLocation(const MachineInstr *MI) const {
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}
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
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unsigned ExtraExprSize) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
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unsigned Reg = RI->getDwarfRegNum(MLoc.getReg(), false);
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if (int Offset = MLoc.getOffset()) {
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if (int Offset = MLoc.getOffset()) {
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@ -759,7 +758,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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// use DW_OP_fbreg.
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// use DW_OP_fbreg.
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unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
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unsigned OffsetSize = Offset ? MCAsmInfo::getSLEB128Size(Offset) : 1;
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OutStreamer.AddComment("Loc expr size");
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1 + OffsetSize + ExtraExprSize);
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EmitInt16(1 + OffsetSize);
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OutStreamer.AddComment(
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
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dwarf::OperationEncodingString(dwarf::DW_OP_fbreg));
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EmitInt8(dwarf::DW_OP_fbreg);
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EmitInt8(dwarf::DW_OP_fbreg);
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@ -774,7 +773,7 @@ void AsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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EmitInt8(dwarf::DW_OP_reg0 + Reg);
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EmitInt8(dwarf::DW_OP_reg0 + Reg);
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} else {
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} else {
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OutStreamer.AddComment("Loc expr size");
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OutStreamer.AddComment("Loc expr size");
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EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg) + ExtraExprSize);
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EmitInt16(1 + MCAsmInfo::getULEB128Size(Reg));
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OutStreamer.AddComment(
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OutStreamer.AddComment(
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dwarf::OperationEncodingString(dwarf::DW_OP_regx));
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dwarf::OperationEncodingString(dwarf::DW_OP_regx));
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EmitInt8(dwarf::DW_OP_regx);
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EmitInt8(dwarf::DW_OP_regx);
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@ -173,11 +173,10 @@ getDebugValueLocation(const MachineInstr *MI) const {
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}
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}
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/// EmitDwarfRegOp - Emit dwarf register operation.
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/// EmitDwarfRegOp - Emit dwarf register operation.
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void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
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unsigned ExtraExprSize) const {
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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const TargetRegisterInfo *RI = TM.getRegisterInfo();
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if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
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if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1)
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AsmPrinter::EmitDwarfRegOp(MLoc, ExtraExprSize);
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AsmPrinter::EmitDwarfRegOp(MLoc);
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else {
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else {
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unsigned Reg = MLoc.getReg();
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unsigned Reg = MLoc.getReg();
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if (Reg >= ARM::S0 && Reg <= ARM::S31) {
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if (Reg >= ARM::S0 && Reg <= ARM::S31) {
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@ -192,7 +191,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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OutStreamer.AddComment("Loc expr size");
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OutStreamer.AddComment("Loc expr size");
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// DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
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// DW_OP_regx + ULEB + DW_OP_bit_piece + ULEB + ULEB
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// 1 + ULEB(Rx) + 1 + 1 + 1
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// 1 + ULEB(Rx) + 1 + 1 + 1
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EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx) + ExtraExprSize);
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EmitInt16(4 + MCAsmInfo::getULEB128Size(Rx));
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OutStreamer.AddComment("DW_OP_regx for S register");
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OutStreamer.AddComment("DW_OP_regx for S register");
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EmitInt8(dwarf::DW_OP_regx);
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EmitInt8(dwarf::DW_OP_regx);
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@ -224,8 +223,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
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// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
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// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8) +
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// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
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// DW_OP_regx + ULEB + DW_OP_piece + ULEB(8);
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// 6 + ULEB(D1) + ULEB(D2)
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// 6 + ULEB(D1) + ULEB(D2)
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EmitInt16(6 + MCAsmInfo::getULEB128Size(D1)
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EmitInt16(6 + MCAsmInfo::getULEB128Size(D1) + MCAsmInfo::getULEB128Size(D2));
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+ MCAsmInfo::getULEB128Size(D2) + ExtraExprSize);
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OutStreamer.AddComment("DW_OP_regx for Q register: D1");
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OutStreamer.AddComment("DW_OP_regx for Q register: D1");
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EmitInt8(dwarf::DW_OP_regx);
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EmitInt8(dwarf::DW_OP_regx);
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@ -90,8 +90,7 @@ public:
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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/// EmitDwarfRegOp - Emit dwarf register operation.
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/// EmitDwarfRegOp - Emit dwarf register operation.
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virtual void EmitDwarfRegOp(const MachineLocation &MLoc,
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virtual void EmitDwarfRegOp(const MachineLocation &MLoc) const;
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unsigned ExtraExprSize = 0) const;
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virtual unsigned getISAEncoding() {
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virtual unsigned getISAEncoding() {
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// ARM/Darwin adds ISA to the DWARF info for each function.
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// ARM/Darwin adds ISA to the DWARF info for each function.
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