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[WebAssembly] Support running without a register allocator in the default CodeGen passes 

This allows backends which don't use a traditional register allocator,
but do need PHI lowering and other passes, to use the default
TargetPassConfig::addFastRegAlloc and
TargetPassConfig::addOptimizedRegAlloc implementations.

Differential Revision: http://reviews.llvm.org/D12691

llvm-svn: 247065
This commit is contained in:
Dan Gohman 2015-09-08 20:36:33 +00:00
parent 88f0d63bea
commit e32c57443f
2 changed files with 19 additions and 51 deletions
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35
llvm/lib/CodeGen/Passes.cpp
View File

@ -704,7 +704,8 @@ void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
addPass(&PHIEliminationID, false); addPass(&PHIEliminationID, false);
addPass(&TwoAddressInstructionPassID, false); addPass(&TwoAddressInstructionPassID, false);
addPass(RegAllocPass); if (RegAllocPass)
addPass(RegAllocPass);
} }
/// Add standard target-independent passes that are tightly coupled with /// Add standard target-independent passes that are tightly coupled with
@ -735,25 +736,27 @@ void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
// PreRA instruction scheduling. // PreRA instruction scheduling.
addPass(&MachineSchedulerID); addPass(&MachineSchedulerID);
// Add the selected register allocation pass. if (RegAllocPass) {
addPass(RegAllocPass); // Add the selected register allocation pass.
addPass(RegAllocPass);
// Allow targets to change the register assignments before rewriting. // Allow targets to change the register assignments before rewriting.
addPreRewrite(); addPreRewrite();
// Finally rewrite virtual registers. // Finally rewrite virtual registers.
addPass(&VirtRegRewriterID); addPass(&VirtRegRewriterID);
// Perform stack slot coloring and post-ra machine LICM. // Perform stack slot coloring and post-ra machine LICM.
// //
// FIXME: Re-enable coloring with register when it's capable of adding // FIXME: Re-enable coloring with register when it's capable of adding
// kill markers. // kill markers.
addPass(&StackSlotColoringID); addPass(&StackSlotColoringID);
// Run post-ra machine LICM to hoist reloads / remats. // Run post-ra machine LICM to hoist reloads / remats.
// //
// FIXME: can this move into MachineLateOptimization? // FIXME: can this move into MachineLateOptimization?
addPass(&PostRAMachineLICMID); addPass(&PostRAMachineLICMID);
}
} }
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//

35
llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
View File

@ -94,15 +94,12 @@ public:
} }
FunctionPass *createTargetRegisterAllocator(bool) override; FunctionPass *createTargetRegisterAllocator(bool) override;
void addFastRegAlloc(FunctionPass *RegAllocPass) override;
void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
void addIRPasses() override; void addIRPasses() override;
bool addPreISel() override; bool addPreISel() override;
bool addInstSelector() override; bool addInstSelector() override;
bool addILPOpts() override; bool addILPOpts() override;
void addPreRegAlloc() override; void addPreRegAlloc() override;
void addRegAllocPasses(bool Optimized);
void addPostRegAlloc() override; void addPostRegAlloc() override;
void addPreSched2() override; void addPreSched2() override;
void addPreEmitPass() override; void addPreEmitPass() override;
@ -124,16 +121,6 @@ FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
return nullptr; // No reg alloc return nullptr; // No reg alloc
} }
void WebAssemblyPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
assert(!RegAllocPass && "WebAssembly uses no regalloc!");
addRegAllocPasses(false);
}
void WebAssemblyPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
assert(!RegAllocPass && "WebAssembly uses no regalloc!");
addRegAllocPasses(true);
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// The following functions are called from lib/CodeGen/Passes.cpp to modify // The following functions are called from lib/CodeGen/Passes.cpp to modify
// the CodeGen pass sequence. // the CodeGen pass sequence.
@ -164,28 +151,6 @@ bool WebAssemblyPassConfig::addILPOpts() { return true; }
void WebAssemblyPassConfig::addPreRegAlloc() {} void WebAssemblyPassConfig::addPreRegAlloc() {}
void WebAssemblyPassConfig::addRegAllocPasses(bool Optimized) {
// This is list is derived from the regalloc pass list used in
// addFastRegAlloc and addOptimizedRegAlloc in lib/CodeGen/Passes.cpp. We
// don't run the actual register allocator, but we do run the passes which
// lower SSA form, so after these passes are complete, we have non-SSA
// virtual registers.
if (Optimized) {
addPass(&ProcessImplicitDefsID);
addPass(&LiveVariablesID);
addPass(&MachineLoopInfoID);
}
addPass(&PHIEliminationID);
addPass(&TwoAddressInstructionPassID, false);
if (Optimized) {
addPass(&RegisterCoalescerID);
addPass(&MachineSchedulerID);
}
}
void WebAssemblyPassConfig::addPostRegAlloc() { void WebAssemblyPassConfig::addPostRegAlloc() {
// FIXME: the following passes dislike virtual registers. Disable them for now // FIXME: the following passes dislike virtual registers. Disable them for now
// so that basic tests can pass. Future patches will remedy this. // so that basic tests can pass. Future patches will remedy this.