replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Use getTargetConstant instead of getConstant since it's meant as an constant operand. 

llvm-svn: 76803
This commit is contained in:
Evan Cheng 2009-07-22 22:03:29 +00:00
parent c510293251
commit e270d4a4dd
5 changed files with 120 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -954,7 +954,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
SDValue ShImmOp = CurDAG->getConstant(ShImm, MVT::i32);
SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
@ -970,7 +970,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
break;
SDValue V = Op.getOperand(0);
ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
SDValue ShImmOp = CurDAG->getConstant(ShImm, MVT::i32);
SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
if (Subtarget->isThumb()) {
SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };

17
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -558,19 +558,20 @@ def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
def LEApcrel : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, pred:$p), Pseudo,
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
[]>;
def LEApcrelJT : AXI1<0x0, (outs GPR:$dst),
(ins i32imm:$label, i32imm:$id, pred:$p),
Pseudo,
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, "
"(${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
[]> {
let Inst{25} = 1;
}

13
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -554,16 +554,17 @@ let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
// assembler.
let Defs = [CPSR] in {
def tLEApcrel : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label),
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmovs $dst, #PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmovs $dst, #${:private}PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
def tLEApcrelJT : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
!strconcat(!strconcat(".set ${:private}PCRELV${:uid},"
" (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+4))\n"),
!strconcat("\tmovs $dst, #PCRELV${:uid}\n",
!strconcat("\tmovs $dst, #${:private}PCRELV${:uid}\n",
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
[]>;
}

13
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -450,18 +450,19 @@ def t2PICADD : T2XI<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
// LEApcrel - Load a pc-relative address into a register without offending the
// assembler.
def t2LEApcrel : T2XI<(outs GPR:$dst), (ins i32imm:$label, pred:$p),
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
!strconcat(!strconcat(".set ${:private}PCRELV${:uid}, ($label-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")),
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
[]>;
def t2LEApcrelJT : T2XI<(outs GPR:$dst),
(ins i32imm:$label, i32imm:$id, pred:$p),
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #PCRELV${:uid}")),
!strconcat(!strconcat(".set ${:private}PCRELV${:uid},"
" (${label}_${id:no_hash}-(",
"${:private}PCRELL${:uid}+8))\n"),
!strconcat("${:private}PCRELL${:uid}:\n\t",
"add$p $dst, pc, #${:private}PCRELV${:uid}")),
[]>;
// ADD rd, sp, #so_imm

95
llvm/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll Normal file
View File

@ -0,0 +1,95 @@
; RUN: llvm-as < %s | llc -march=arm
%struct.cli_ac_alt = type { i8, i8*, i16, i16, %struct.cli_ac_alt* }
%struct.cli_ac_node = type { i8, i8, %struct.cli_ac_patt*, %struct.cli_ac_node**, %struct.cli_ac_node* }
%struct.cli_ac_patt = type { i16*, i16*, i16, i16, i8, i32, i32, i8*, i8*, i32, i16, i16, i16, i16, %struct.cli_ac_alt**, i8, i16, %struct.cli_ac_patt*, %struct.cli_ac_patt* }
%struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 }
%struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 }
define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind {
entry:
br i1 undef, label %bb126, label %bb1
bb1: ; preds = %entry
br i1 undef, label %cli_calloc.exit.thread, label %cli_calloc.exit
cli_calloc.exit.thread: ; preds = %bb1
ret i32 -114
cli_calloc.exit: ; preds = %bb1
br i1 undef, label %bb52, label %bb4
bb4: ; preds = %cli_calloc.exit
br i1 undef, label %bb.i, label %bb1.i3
bb.i: ; preds = %bb4
unreachable
bb1.i3: ; preds = %bb4
br i1 undef, label %bb2.i4, label %cli_strdup.exit
bb2.i4: ; preds = %bb1.i3
ret i32 -114
cli_strdup.exit: ; preds = %bb1.i3
br i1 undef, label %cli_calloc.exit54.thread, label %cli_calloc.exit54
cli_calloc.exit54.thread: ; preds = %cli_strdup.exit
ret i32 -114
cli_calloc.exit54: ; preds = %cli_strdup.exit
br label %bb45
cli_calloc.exit70.thread: ; preds = %bb45
unreachable
cli_calloc.exit70: ; preds = %bb45
br i1 undef, label %bb.i83, label %bb1.i84
bb.i83: ; preds = %cli_calloc.exit70
unreachable
bb1.i84: ; preds = %cli_calloc.exit70
br i1 undef, label %bb2.i85, label %bb17
bb2.i85: ; preds = %bb1.i84
unreachable
bb17: ; preds = %bb1.i84
br i1 undef, label %bb22, label %bb.nph
bb.nph: ; preds = %bb17
br label %bb18
bb18: ; preds = %bb18, %bb.nph
br i1 undef, label %bb18, label %bb22
bb22: ; preds = %bb18, %bb17
%0 = getelementptr i8* null, i32 10 ; <i8*> [#uses=1]
%1 = bitcast i8* %0 to i16* ; <i16*> [#uses=1]
%2 = load i16* %1, align 2 ; <i16> [#uses=1]
%3 = add i16 %2, 1 ; <i16> [#uses=1]
%4 = zext i16 %3 to i32 ; <i32> [#uses=1]
%5 = mul i32 %4, 3 ; <i32> [#uses=1]
%6 = add i32 %5, -1 ; <i32> [#uses=1]
%7 = icmp eq i32 %6, undef ; <i1> [#uses=1]
br i1 %7, label %bb25, label %bb43.preheader
bb43.preheader: ; preds = %bb22
br i1 undef, label %bb28, label %bb45
bb25: ; preds = %bb22
unreachable
bb28: ; preds = %bb43.preheader
unreachable
bb45: ; preds = %bb43.preheader, %cli_calloc.exit54
br i1 undef, label %cli_calloc.exit70.thread, label %cli_calloc.exit70
bb52: ; preds = %cli_calloc.exit
unreachable
bb126: ; preds = %entry
ret i32 -117
}