From e2347df24dc1cf27f85b04a5ac3245b0a389651a Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@gmail.com>
Date: Thu, 20 Feb 2014 07:59:43 +0000
Subject: [PATCH] [x86] Switch PAUSE instruction to use XS prefix instead of
 HasREPPrefix. Remove HasREPPrefix support from disassembler table generator
 since its now only used by CodeGenOnly instructions.

llvm-svn: 201767
---
 llvm/lib/Target/X86/X86InstrFormats.td       | 1 +
 llvm/lib/Target/X86/X86InstrSSE.td           | 2 +-
 llvm/utils/TableGen/X86RecognizableInstr.cpp | 3 +--
 llvm/utils/TableGen/X86RecognizableInstr.h   | 2 --
 4 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/X86/X86InstrFormats.td b/llvm/lib/Target/X86/X86InstrFormats.td
index 0f6533dcea5f..9b9480c1f0c2 100644
--- a/llvm/lib/Target/X86/X86InstrFormats.td
+++ b/llvm/lib/Target/X86/X86InstrFormats.td
@@ -158,6 +158,7 @@ class TA     { Map OpMap = TA; }
 class XOP8   { Map OpMap = XOP8; Prefix OpPrefix = PS; }
 class XOP9   { Map OpMap = XOP9; Prefix OpPrefix = PS; }
 class XOPA   { Map OpMap = XOPA; Prefix OpPrefix = PS; }
+class OBXS   { Prefix OpPrefix = XS; }
 class PS   : TB { Prefix OpPrefix = PS; }
 class PD   : TB { Prefix OpPrefix = PD; }
 class XD   : TB { Prefix OpPrefix = XD; }
diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index c8233e03f52d..fb2ac6620fd0 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -3728,7 +3728,7 @@ def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
 // was introduced with SSE2, it's backward compatible.
 def PAUSE : I<0x90, RawFrm, (outs), (ins),  
               "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>, 
-              REP, Requires<[HasSSE2]>;
+              OBXS, Requires<[HasSSE2]>;
 
 // Load, store, and memory fence
 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp
index 0ebdd592b13c..9ea0bf7abcc4 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.cpp
+++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp
@@ -203,7 +203,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
   HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
   HasEVEX_KZ       = Rec->getValueAsBit("hasEVEX_Z");
   HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
-  HasREPPrefix     = Rec->getValueAsBit("hasREPPrefix");
   IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
   ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
 
@@ -433,7 +432,7 @@ InstructionContext RecognizableInstr::insnContext() const {
       insnContext = IC_ADSIZE;
     else if (OpPrefix == X86Local::XD)
       insnContext = IC_XD;
-    else if (OpPrefix == X86Local::XS || HasREPPrefix)
+    else if (OpPrefix == X86Local::XS)
       insnContext = IC_XS;
     else
       insnContext = IC;
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h
index 5866566ac02c..77286bc43361 100644
--- a/llvm/utils/TableGen/X86RecognizableInstr.h
+++ b/llvm/utils/TableGen/X86RecognizableInstr.h
@@ -74,8 +74,6 @@ private:
   bool HasEVEX_KZ;
   /// The hasEVEX_B field from the record
   bool HasEVEX_B;
-  /// The hasREPPrefix field from the record
-  bool HasREPPrefix;
   /// The isCodeGenOnly field from the record
   bool IsCodeGenOnly;
   /// The ForceDisassemble field from the record