To handle s* registers in emitVFPLoadStoreMultipleInstruction().
Fixing http://llvm.org/bugs/show_bug.cgi?id=7221. llvm-svn: 104652
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@ -146,11 +146,11 @@ namespace {
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return getMachineOpValue(MI, MI.getOperand(OpIdx));
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}
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/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
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/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
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/// machine operand requires relocation, record the relocation and return zero.
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unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
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unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
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unsigned Reloc);
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unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
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unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
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unsigned Reloc) {
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return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
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}
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@ -227,12 +227,12 @@ unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
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return 0;
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}
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/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
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/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
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/// machine operand requires relocation, record the relocation and return zero.
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unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
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const MachineOperand &MO,
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const MachineOperand &MO,
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unsigned Reloc) {
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assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
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assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
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&& "Relocation to this function should be for movt or movw");
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if (MO.isImm())
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@ -1459,7 +1459,12 @@ ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
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break;
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++NumRegs;
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}
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Binary |= NumRegs * 2;
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// Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
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// Otherwise, it will be 0, in the case of 32-bit registers.
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if(Binary & 0x100)
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Binary |= NumRegs * 2;
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else
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Binary |= NumRegs;
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emitWordLE(Binary);
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}
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