Move X86 instruction parsing into X86/AsmParser.
llvm-svn: 77384
This commit is contained in:
parent
e2d3dd66f1
commit
e1fdb0e8ce
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@ -43,8 +43,7 @@ public:
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/// \param Name - The instruction name.
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/// \param Name - The instruction name.
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/// \param Inst [out] - On success, the parsed instruction.
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/// \param Inst [out] - On success, the parsed instruction.
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/// \return True on failure.
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/// \return True on failure.
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virtual bool ParseInstruction(MCAsmParser &AP, const StringRef &Name,
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virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst) = 0;
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MCInst &Inst) = 0;
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};
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};
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} // End llvm namespace
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} // End llvm namespace
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@ -9,52 +9,297 @@
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#include "X86.h"
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#include "X86.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAsmLexer.h"
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#include "llvm/MC/MCAsmLexer.h"
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#include "llvm/MC/MCAsmParser.h"
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#include "llvm/MC/MCAsmParser.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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#include "llvm/Target/TargetAsmParser.h"
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using namespace llvm;
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using namespace llvm;
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namespace {
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namespace {
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struct X86Operand {
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class X86Operand;
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class X86ATTAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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private:
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bool MatchInstruction(const StringRef &Name,
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llvm::SmallVector<X86Operand, 3> &Operands,
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MCInst &Inst);
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(X86Operand &Op);
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bool ParseOperand(X86Operand &Op);
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bool ParseMemOperand(X86Operand &Op);
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public:
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X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: TargetAsmParser(T), Parser(_Parser) {}
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virtual bool ParseInstruction(const StringRef &Name, MCInst &Inst);
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};
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand {
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enum {
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Register,
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Immediate,
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Memory
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} Kind;
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union {
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struct {
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unsigned RegNo;
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} Reg;
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struct {
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MCValue Val;
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} Imm;
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struct {
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unsigned SegReg;
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MCValue Disp;
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unsigned BaseReg;
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unsigned IndexReg;
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unsigned Scale;
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} Mem;
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};
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};
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class X86ATTAsmParser : public TargetAsmParser {
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unsigned getReg() const {
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MCAsmParser &Parser;
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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private:
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static X86Operand CreateReg(unsigned RegNo) {
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bool ParseOperand(X86Operand &Op);
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X86Operand Res;
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Res.Kind = Register;
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bool MatchInstruction(const StringRef &Name,
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Res.Reg.RegNo = RegNo;
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llvm::SmallVector<X86Operand, 3> &Operands,
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return Res;
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MCInst &Inst);
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}
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static X86Operand CreateImm(MCValue Val) {
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X86Operand Res;
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Res.Kind = Immediate;
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Res.Imm.Val = Val;
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return Res;
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}
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static X86Operand CreateMem(unsigned SegReg, MCValue Disp, unsigned BaseReg,
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unsigned IndexReg, unsigned Scale) {
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// If there is no index register, we should never have a scale, and we
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// should always have a scale (in {1,2,4,8}) if we do.
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assert(((Scale == 0 && !IndexReg) ||
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(IndexReg && (Scale == 1 || Scale == 2 ||
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Scale == 4 || Scale == 8))) &&
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"Invalid scale!");
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X86Operand Res;
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Res.Kind = Memory;
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Res.Mem.SegReg = SegReg;
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Res.Mem.Disp = Disp;
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Res.Mem.BaseReg = BaseReg;
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Res.Mem.IndexReg = IndexReg;
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Res.Mem.Scale = Scale;
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return Res;
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}
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};
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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}
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public:
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//
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X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: TargetAsmParser(T), Parser(_Parser) {}
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bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
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assert(getLexer().is(AsmToken::Register) && "Invalid token kind!");
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virtual bool ParseInstruction(MCAsmParser &AP, const StringRef &Name,
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MCInst &Inst);
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// FIXME: Decode register number.
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};
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Op = X86Operand::CreateReg(123);
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getLexer().Lex(); // Eat register token.
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return false;
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}
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}
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bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
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bool X86ATTAsmParser::ParseOperand(X86Operand &Op) {
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return true;
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switch (getLexer().getKind()) {
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default:
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return ParseMemOperand(Op);
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case AsmToken::Register:
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// FIXME: if a segment register, this could either be just the seg reg, or
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// the start of a memory operand.
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return ParseRegister(Op);
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case AsmToken::Dollar: {
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// $42 -> immediate.
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getLexer().Lex();
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MCValue Val;
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if (getParser().ParseRelocatableExpression(Val))
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return true;
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Op = X86Operand::CreateImm(Val);
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return false;
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}
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case AsmToken::Star: {
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getLexer().Lex(); // Eat the star.
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if (getLexer().is(AsmToken::Register)) {
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if (ParseRegister(Op))
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return true;
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} else if (ParseMemOperand(Op))
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return true;
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// FIXME: Note the '*' in the operand for use by the matcher.
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return false;
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}
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}
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}
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}
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bool
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/// ParseMemOperand: segment: disp(basereg, indexreg, scale)
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X86ATTAsmParser::MatchInstruction(const StringRef &Name,
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bool X86ATTAsmParser::ParseMemOperand(X86Operand &Op) {
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// FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
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unsigned SegReg = 0;
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// We have to disambiguate a parenthesized expression "(4+5)" from the start
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// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
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// only way to do this without lookahead is to eat the ( and see what is after
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// it.
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MCValue Disp = MCValue::get(0, 0, 0);
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if (getLexer().isNot(AsmToken::LParen)) {
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if (getParser().ParseRelocatableExpression(Disp)) return true;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
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return false;
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}
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// Eat the '('.
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getLexer().Lex();
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} else {
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// Okay, we have a '('. We don't know if this is an expression or not, but
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// so we have to eat the ( to see beyond it.
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getLexer().Lex(); // Eat the '('.
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if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
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// Nothing to do here, fall into the code below with the '(' part of the
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// memory operand consumed.
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} else {
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// It must be an parenthesized expression, parse it now.
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if (getParser().ParseParenRelocatableExpression(Disp))
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return true;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
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return false;
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}
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// Eat the '('.
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getLexer().Lex();
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}
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}
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// If we reached here, then we just ate the ( of the memory operand. Process
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// the rest of the memory operand.
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unsigned BaseReg = 0, IndexReg = 0, Scale = 0;
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if (getLexer().is(AsmToken::Register)) {
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if (ParseRegister(Op))
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return true;
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BaseReg = Op.getReg();
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}
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if (getLexer().is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat the comma.
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// Following the comma we should have either an index register, or a scale
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// value. We don't support the later form, but we want to parse it
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// correctly.
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//
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// Not that even though it would be completely consistent to support syntax
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// like "1(%eax,,1)", the assembler doesn't.
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if (getLexer().is(AsmToken::Register)) {
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if (ParseRegister(Op))
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return true;
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IndexReg = Op.getReg();
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Scale = 1; // If not specified, the scale defaults to 1.
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if (getLexer().isNot(AsmToken::RParen)) {
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// Parse the scale amount:
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// ::= ',' [scale-expression]
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if (getLexer().isNot(AsmToken::Comma))
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return true;
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getLexer().Lex(); // Eat the comma.
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if (getLexer().isNot(AsmToken::RParen)) {
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SMLoc Loc = getLexer().getTok().getLoc();
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int64_t ScaleVal;
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if (getParser().ParseAbsoluteExpression(ScaleVal))
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return true;
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// Validate the scale amount.
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if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
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return Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
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Scale = (unsigned)ScaleVal;
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}
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}
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} else if (getLexer().isNot(AsmToken::RParen)) {
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// Otherwise we have the unsupported form of a scale amount without an
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// index.
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SMLoc Loc = getLexer().getTok().getLoc();
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int64_t Value;
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if (getParser().ParseAbsoluteExpression(Value))
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return true;
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return Error(Loc, "cannot have scale factor without index register");
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}
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}
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// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
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if (getLexer().isNot(AsmToken::RParen))
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return Error(getLexer().getTok().getLoc(),
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"unexpected token in memory operand");
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getLexer().Lex(); // Eat the ')'.
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Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
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return false;
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}
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bool
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X86ATTAsmParser::MatchInstruction(const StringRef &Name,
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llvm::SmallVector<X86Operand, 3> &Operands,
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llvm::SmallVector<X86Operand, 3> &Operands,
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MCInst &Inst) {
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MCInst &Inst) {
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return false;
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return false;
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}
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}
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bool X86ATTAsmParser::ParseInstruction(MCAsmParser &AP, const StringRef &Name,
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bool X86ATTAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
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MCInst &Inst) {
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llvm::SmallVector<X86Operand, 3> Operands;
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llvm::SmallVector<X86Operand, 3> Operands;
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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Operands.push_back(X86Operand());
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if (ParseOperand(Operands.back()))
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return true;
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while (getLexer().is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat the comma.
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// Parse and remember the operand.
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Operands.push_back(X86Operand());
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if (ParseOperand(Operands.back()))
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return true;
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}
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}
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return MatchInstruction(Name, Operands, Inst);
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return MatchInstruction(Name, Operands, Inst);
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}
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}
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@ -551,8 +551,7 @@ bool AsmParser::ParseStatement() {
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}
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}
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MCInst Inst;
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MCInst Inst;
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if (ParseX86InstOperands(IDVal, Inst) &&
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if (getTargetParser().ParseInstruction(IDVal, Inst))
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getTargetParser().ParseInstruction(*this, IDVal, Inst))
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return true;
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return true;
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if (Lexer.isNot(AsmToken::EndOfStatement))
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if (Lexer.isNot(AsmToken::EndOfStatement))
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@ -28,9 +28,6 @@ class TargetAsmParser;
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class Twine;
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class Twine;
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class AsmParser : public MCAsmParser {
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class AsmParser : public MCAsmParser {
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public:
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struct X86Operand;
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private:
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private:
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AsmLexer Lexer;
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AsmLexer Lexer;
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MCContext &Ctx;
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MCContext &Ctx;
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@ -88,12 +85,6 @@ private:
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bool ParseBinOpRHS(unsigned Precedence, AsmExpr *&Res);
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bool ParseBinOpRHS(unsigned Precedence, AsmExpr *&Res);
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bool ParseParenExpr(AsmExpr *&Res);
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bool ParseParenExpr(AsmExpr *&Res);
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// X86 specific.
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bool ParseX86InstOperands(const StringRef &InstName, MCInst &Inst);
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bool ParseX86Operand(X86Operand &Op);
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bool ParseX86MemOperand(X86Operand &Op);
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bool ParseX86Register(X86Operand &Op);
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// Directive Parsing.
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// Directive Parsing.
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bool ParseDirectiveDarwinSection(); // Darwin specific ".section".
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bool ParseDirectiveDarwinSection(); // Darwin specific ".section".
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bool ParseDirectiveSectionSwitch(const char *Section,
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bool ParseDirectiveSectionSwitch(const char *Section,
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@ -1,267 +0,0 @@
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//===- MC-X86Specific.cpp - X86-Specific code for MC ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements X86-specific parsing, encoding and decoding stuff for
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// MC.
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//
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//===----------------------------------------------------------------------===//
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#include "AsmParser.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/SourceMgr.h"
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using namespace llvm;
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/// X86Operand - Instances of this class represent one X86 machine instruction.
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struct AsmParser::X86Operand {
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enum {
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|
||||||
Register,
|
|
||||||
Immediate,
|
|
||||||
Memory
|
|
||||||
} Kind;
|
|
||||||
|
|
||||||
union {
|
|
||||||
struct {
|
|
||||||
unsigned RegNo;
|
|
||||||
} Reg;
|
|
||||||
|
|
||||||
struct {
|
|
||||||
MCValue Val;
|
|
||||||
} Imm;
|
|
||||||
|
|
||||||
struct {
|
|
||||||
unsigned SegReg;
|
|
||||||
MCValue Disp;
|
|
||||||
unsigned BaseReg;
|
|
||||||
unsigned IndexReg;
|
|
||||||
unsigned Scale;
|
|
||||||
} Mem;
|
|
||||||
};
|
|
||||||
|
|
||||||
unsigned getReg() const {
|
|
||||||
assert(Kind == Register && "Invalid access!");
|
|
||||||
return Reg.RegNo;
|
|
||||||
}
|
|
||||||
|
|
||||||
static X86Operand CreateReg(unsigned RegNo) {
|
|
||||||
X86Operand Res;
|
|
||||||
Res.Kind = Register;
|
|
||||||
Res.Reg.RegNo = RegNo;
|
|
||||||
return Res;
|
|
||||||
}
|
|
||||||
static X86Operand CreateImm(MCValue Val) {
|
|
||||||
X86Operand Res;
|
|
||||||
Res.Kind = Immediate;
|
|
||||||
Res.Imm.Val = Val;
|
|
||||||
return Res;
|
|
||||||
}
|
|
||||||
static X86Operand CreateMem(unsigned SegReg, MCValue Disp, unsigned BaseReg,
|
|
||||||
unsigned IndexReg, unsigned Scale) {
|
|
||||||
// If there is no index register, we should never have a scale, and we
|
|
||||||
// should always have a scale (in {1,2,4,8}) if we do.
|
|
||||||
assert(((Scale == 0 && !IndexReg) ||
|
|
||||||
(IndexReg && (Scale == 1 || Scale == 2 ||
|
|
||||||
Scale == 4 || Scale == 8))) &&
|
|
||||||
"Invalid scale!");
|
|
||||||
X86Operand Res;
|
|
||||||
Res.Kind = Memory;
|
|
||||||
Res.Mem.SegReg = SegReg;
|
|
||||||
Res.Mem.Disp = Disp;
|
|
||||||
Res.Mem.BaseReg = BaseReg;
|
|
||||||
Res.Mem.IndexReg = IndexReg;
|
|
||||||
Res.Mem.Scale = Scale;
|
|
||||||
return Res;
|
|
||||||
}
|
|
||||||
};
|
|
||||||
|
|
||||||
bool AsmParser::ParseX86Register(X86Operand &Op) {
|
|
||||||
assert(getLexer().is(AsmToken::Register) && "Invalid token kind!");
|
|
||||||
|
|
||||||
// FIXME: Decode register number.
|
|
||||||
Op = X86Operand::CreateReg(123);
|
|
||||||
getLexer().Lex(); // Eat register token.
|
|
||||||
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
bool AsmParser::ParseX86Operand(X86Operand &Op) {
|
|
||||||
switch (getLexer().getKind()) {
|
|
||||||
default:
|
|
||||||
return ParseX86MemOperand(Op);
|
|
||||||
case AsmToken::Register:
|
|
||||||
// FIXME: if a segment register, this could either be just the seg reg, or
|
|
||||||
// the start of a memory operand.
|
|
||||||
return ParseX86Register(Op);
|
|
||||||
case AsmToken::Dollar: {
|
|
||||||
// $42 -> immediate.
|
|
||||||
getLexer().Lex();
|
|
||||||
MCValue Val;
|
|
||||||
if (ParseRelocatableExpression(Val))
|
|
||||||
return true;
|
|
||||||
Op = X86Operand::CreateImm(Val);
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
case AsmToken::Star: {
|
|
||||||
getLexer().Lex(); // Eat the star.
|
|
||||||
|
|
||||||
if (getLexer().is(AsmToken::Register)) {
|
|
||||||
if (ParseX86Register(Op))
|
|
||||||
return true;
|
|
||||||
} else if (ParseX86MemOperand(Op))
|
|
||||||
return true;
|
|
||||||
|
|
||||||
// FIXME: Note the '*' in the operand for use by the matcher.
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// ParseX86MemOperand: segment: disp(basereg, indexreg, scale)
|
|
||||||
bool AsmParser::ParseX86MemOperand(X86Operand &Op) {
|
|
||||||
// FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
|
|
||||||
unsigned SegReg = 0;
|
|
||||||
|
|
||||||
// We have to disambiguate a parenthesized expression "(4+5)" from the start
|
|
||||||
// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
|
|
||||||
// only way to do this without lookahead is to eat the ( and see what is after
|
|
||||||
// it.
|
|
||||||
MCValue Disp = MCValue::get(0, 0, 0);
|
|
||||||
if (getLexer().isNot(AsmToken::LParen)) {
|
|
||||||
if (ParseRelocatableExpression(Disp)) return true;
|
|
||||||
|
|
||||||
// After parsing the base expression we could either have a parenthesized
|
|
||||||
// memory address or not. If not, return now. If so, eat the (.
|
|
||||||
if (getLexer().isNot(AsmToken::LParen)) {
|
|
||||||
Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Eat the '('.
|
|
||||||
getLexer().Lex();
|
|
||||||
} else {
|
|
||||||
// Okay, we have a '('. We don't know if this is an expression or not, but
|
|
||||||
// so we have to eat the ( to see beyond it.
|
|
||||||
getLexer().Lex(); // Eat the '('.
|
|
||||||
|
|
||||||
if (getLexer().is(AsmToken::Register) || getLexer().is(AsmToken::Comma)) {
|
|
||||||
// Nothing to do here, fall into the code below with the '(' part of the
|
|
||||||
// memory operand consumed.
|
|
||||||
} else {
|
|
||||||
// It must be an parenthesized expression, parse it now.
|
|
||||||
if (ParseParenRelocatableExpression(Disp))
|
|
||||||
return true;
|
|
||||||
|
|
||||||
// After parsing the base expression we could either have a parenthesized
|
|
||||||
// memory address or not. If not, return now. If so, eat the (.
|
|
||||||
if (getLexer().isNot(AsmToken::LParen)) {
|
|
||||||
Op = X86Operand::CreateMem(SegReg, Disp, 0, 0, 0);
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Eat the '('.
|
|
||||||
getLexer().Lex();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// If we reached here, then we just ate the ( of the memory operand. Process
|
|
||||||
// the rest of the memory operand.
|
|
||||||
unsigned BaseReg = 0, IndexReg = 0, Scale = 0;
|
|
||||||
|
|
||||||
if (getLexer().is(AsmToken::Register)) {
|
|
||||||
if (ParseX86Register(Op))
|
|
||||||
return true;
|
|
||||||
BaseReg = Op.getReg();
|
|
||||||
}
|
|
||||||
|
|
||||||
if (getLexer().is(AsmToken::Comma)) {
|
|
||||||
getLexer().Lex(); // Eat the comma.
|
|
||||||
|
|
||||||
// Following the comma we should have either an index register, or a scale
|
|
||||||
// value. We don't support the later form, but we want to parse it
|
|
||||||
// correctly.
|
|
||||||
//
|
|
||||||
// Not that even though it would be completely consistent to support syntax
|
|
||||||
// like "1(%eax,,1)", the assembler doesn't.
|
|
||||||
if (getLexer().is(AsmToken::Register)) {
|
|
||||||
if (ParseX86Register(Op))
|
|
||||||
return true;
|
|
||||||
IndexReg = Op.getReg();
|
|
||||||
Scale = 1; // If not specified, the scale defaults to 1.
|
|
||||||
|
|
||||||
if (getLexer().isNot(AsmToken::RParen)) {
|
|
||||||
// Parse the scale amount:
|
|
||||||
// ::= ',' [scale-expression]
|
|
||||||
if (getLexer().isNot(AsmToken::Comma))
|
|
||||||
return true;
|
|
||||||
getLexer().Lex(); // Eat the comma.
|
|
||||||
|
|
||||||
if (getLexer().isNot(AsmToken::RParen)) {
|
|
||||||
int64_t ScaleVal;
|
|
||||||
if (ParseAbsoluteExpression(ScaleVal))
|
|
||||||
return true;
|
|
||||||
|
|
||||||
// Validate the scale amount.
|
|
||||||
if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8)
|
|
||||||
return TokError("scale factor in address must be 1, 2, 4 or 8");
|
|
||||||
Scale = (unsigned)ScaleVal;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else if (getLexer().isNot(AsmToken::RParen)) {
|
|
||||||
// Otherwise we have the unsupported form of a scale amount without an
|
|
||||||
// index.
|
|
||||||
SMLoc Loc = getLexer().getTok().getLoc();
|
|
||||||
|
|
||||||
int64_t Value;
|
|
||||||
if (ParseAbsoluteExpression(Value))
|
|
||||||
return true;
|
|
||||||
|
|
||||||
return Error(Loc, "cannot have scale factor without index register");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
|
|
||||||
if (getLexer().isNot(AsmToken::RParen))
|
|
||||||
return TokError("unexpected token in memory operand");
|
|
||||||
getLexer().Lex(); // Eat the ')'.
|
|
||||||
|
|
||||||
Op = X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale);
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/// MatchX86Inst - Convert a parsed instruction name and operand list into a
|
|
||||||
/// concrete instruction.
|
|
||||||
static bool MatchX86Inst(const StringRef &Name,
|
|
||||||
llvm::SmallVector<AsmParser::X86Operand, 3> &Operands,
|
|
||||||
MCInst &Inst) {
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
|
|
||||||
/// ParseX86InstOperands - Parse the operands of an X86 instruction and return
|
|
||||||
/// them as the operands of an MCInst.
|
|
||||||
bool AsmParser::ParseX86InstOperands(const StringRef &InstName, MCInst &Inst) {
|
|
||||||
llvm::SmallVector<X86Operand, 3> Operands;
|
|
||||||
|
|
||||||
if (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
||||||
// Read the first operand.
|
|
||||||
Operands.push_back(X86Operand());
|
|
||||||
if (ParseX86Operand(Operands.back()))
|
|
||||||
return true;
|
|
||||||
|
|
||||||
while (getLexer().is(AsmToken::Comma)) {
|
|
||||||
getLexer().Lex(); // Eat the comma.
|
|
||||||
|
|
||||||
// Parse and remember the operand.
|
|
||||||
Operands.push_back(X86Operand());
|
|
||||||
if (ParseX86Operand(Operands.back()))
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return MatchX86Inst(InstName, Operands, Inst);
|
|
||||||
}
|
|
|
@ -196,6 +196,7 @@ static int AssembleInput(const char *ProgName) {
|
||||||
OwningPtr<TargetAsmParser> TAP(GetTargetAsmParser(ProgName, Parser));
|
OwningPtr<TargetAsmParser> TAP(GetTargetAsmParser(ProgName, Parser));
|
||||||
if (!TAP)
|
if (!TAP)
|
||||||
return 1;
|
return 1;
|
||||||
|
Parser.setTargetParser(*TAP.get());
|
||||||
return Parser.Run();
|
return Parser.Run();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue