parent
95b714c749
commit
e1f1da30f4
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@ -124,17 +124,16 @@ AMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const {
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MachineBasicBlock *MBB = MI->getParent();
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int OffsetOpIdx =
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AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::addr);
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int OffsetOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::addr);
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// addr is a custom operand with multiple MI operands, and only the
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// first MI operand is given a name.
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int RegOpIdx = OffsetOpIdx + 1;
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int ChanOpIdx =
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AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::chan);
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int ChanOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::chan);
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if (isRegisterLoad(*MI)) {
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int DstOpIdx =
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AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
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int DstOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::dst);
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unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
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unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
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unsigned Address = calculateIndirectAddress(RegIndex, Channel);
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@ -147,8 +146,8 @@ bool AMDGPUInstrInfo::expandPostRAPseudo (MachineBasicBlock::iterator MI) const
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Address, OffsetReg);
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}
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} else if (isRegisterStore(*MI)) {
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int ValOpIdx =
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AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::val);
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int ValOpIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(),
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AMDGPU::OpName::val);
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AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
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unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
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unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
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