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@ -34,15 +34,15 @@ using namespace llvm;
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//===----------------------------------------------------------------------===//
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namespace {
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/// MachineSchedulerPass runs after coalescing and before register allocation.
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class MachineSchedulerPass : public MachineFunctionPass {
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/// MachineScheduler runs after coalescing and before register allocation.
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class MachineScheduler : public MachineFunctionPass {
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public:
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const MachineLoopInfo *MLI;
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const MachineDominatorTree *MDT;
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MachineSchedulerPass();
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MachineScheduler();
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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@ -56,11 +56,11 @@ public:
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};
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} // namespace
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char MachineSchedulerPass::ID = 0;
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char MachineScheduler::ID = 0;
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char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
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char &llvm::MachineSchedulerID = MachineScheduler::ID;
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INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
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INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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@ -68,15 +68,15 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
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INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
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INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
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INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
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INITIALIZE_PASS_END(MachineScheduler, "misched",
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"Machine Instruction Scheduler", false, false)
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MachineSchedulerPass::MachineSchedulerPass()
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MachineScheduler::MachineScheduler()
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: MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
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initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
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initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
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}
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void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
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void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequiredID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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@ -102,7 +102,7 @@ namespace {
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/// schedulers.
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class MachineSchedRegistry : public MachinePassRegistryNode {
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public:
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
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typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
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// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
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typedef ScheduleDAGCtor FunctionPassCtor;
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@ -137,7 +137,7 @@ public:
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MachinePassRegistry MachineSchedRegistry::Registry;
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
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/// MachineSchedOpt allows command line selection of the scheduler.
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static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
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@ -147,45 +147,22 @@ MachineSchedOpt("misched",
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cl::desc("Machine instruction scheduler to use"));
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//===----------------------------------------------------------------------===//
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// Machine Instruction Scheduling Implementation
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// Machine Instruction Scheduling Common Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// MachineScheduler is an implementation of ScheduleDAGInstrs that schedules
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/// machine instructions while updating LiveIntervals.
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class MachineScheduler : public ScheduleDAGInstrs {
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MachineSchedulerPass *Pass;
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class ScheduleTopDownLive : public ScheduleDAGInstrs {
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protected:
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MachineScheduler *Pass;
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public:
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MachineScheduler(MachineSchedulerPass *P):
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ScheduleTopDownLive(MachineScheduler *P):
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ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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virtual void Schedule();
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};
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} // namespace
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
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return new MachineScheduler(P);
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}
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static MachineSchedRegistry
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SchedDefaultRegistry("default", "Activate the scheduler pass, "
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"but don't reorder instructions",
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createDefaultMachineSched);
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void MachineScheduler::Schedule() {
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BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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// TODO: Put interesting things here.
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}
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bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
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bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
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// Initialize the context of the pass.
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MF = &mf;
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MLI = &getAnalysis<MachineLoopInfo>();
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@ -241,10 +218,45 @@ bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
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return true;
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}
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void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
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void MachineScheduler::print(raw_ostream &O, const Module* m) const {
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// unimplemented
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}
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//===----------------------------------------------------------------------===//
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// Placeholder for extending the machine instruction scheduler.
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//===----------------------------------------------------------------------===//
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namespace {
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class DefaultMachineScheduler : public ScheduleTopDownLive {
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public:
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DefaultMachineScheduler(MachineScheduler *P):
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ScheduleTopDownLive(P) {}
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void Schedule();
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};
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} // namespace
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static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
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return new DefaultMachineScheduler(P);
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}
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static MachineSchedRegistry
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SchedDefaultRegistry("default", "Activate the scheduler pass, "
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"but don't reorder instructions",
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createDefaultMachineSched);
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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void DefaultMachineScheduler::Schedule() {
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BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(this));
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// TODO: Put interesting things here.
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}
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//===----------------------------------------------------------------------===//
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// Machine Instruction Shuffler for Correctness Testing
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//===----------------------------------------------------------------------===//
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@ -252,11 +264,11 @@ void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
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#ifndef NDEBUG
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namespace {
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/// Reorder instructions as much as possible.
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class InstructionShuffler : public ScheduleDAGInstrs {
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MachineSchedulerPass *Pass;
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class InstructionShuffler : public ScheduleTopDownLive {
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MachineScheduler *Pass;
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public:
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InstructionShuffler(MachineSchedulerPass *P):
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ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
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InstructionShuffler(MachineScheduler *P):
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ScheduleTopDownLive(P) {}
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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@ -266,7 +278,7 @@ public:
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};
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} // namespace
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static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
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static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
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return new InstructionShuffler(P);
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}
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static MachineSchedRegistry ShufflerRegistry("shuffle",
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