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Renamed MachineScheduler to ScheduleTopDownLive. 

Responding to code review.

llvm-svn: 148290
This commit is contained in:
Andrew Trick 2012-01-17 06:55:03 +00:00
parent 8093eac51d
commit e1c034fefe
6 changed files with 65 additions and 53 deletions
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2
llvm/include/llvm/CodeGen/Passes.h
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@ -85,7 +85,7 @@ namespace llvm {
extern char &RegisterCoalescerPassID;
/// MachineScheduler pass - This pass schedules machine instructions.
extern char &MachineSchedulerPassID;
extern char &MachineSchedulerID;
/// SpillPlacement analysis. Suggest optimal placement of spill code between
/// basic blocks.

2
llvm/include/llvm/InitializePasses.h
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@ -156,7 +156,7 @@ void initializeMachineLICMPass(PassRegistry&);
void initializeMachineLoopInfoPass(PassRegistry&);
void initializeMachineLoopRangesPass(PassRegistry&);
void initializeMachineModuleInfoPass(PassRegistry&);
void initializeMachineSchedulerPassPass(PassRegistry&);
void initializeMachineSchedulerPass(PassRegistry&);
void initializeMachineSinkingPass(PassRegistry&);
void initializeMachineVerifierPassPass(PassRegistry&);
void initializeMemCpyOptPass(PassRegistry&);

2
llvm/lib/CodeGen/CodeGen.cpp
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@ -43,7 +43,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeProcessImplicitDefsPass(Registry);
initializePEIPass(Registry);
initializeRegisterCoalescerPass(Registry);
initializeMachineSchedulerPassPass(Registry);
initializeMachineSchedulerPass(Registry);
initializeRenderMachineFunctionPass(Registry);
initializeSlotIndexesPass(Registry);
initializeStackProtectorPass(Registry);

106
llvm/lib/CodeGen/MachineScheduler.cpp
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@ -34,15 +34,15 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
namespace {
/// MachineSchedulerPass runs after coalescing and before register allocation.
class MachineSchedulerPass : public MachineFunctionPass {
/// MachineScheduler runs after coalescing and before register allocation.
class MachineScheduler : public MachineFunctionPass {
public:
MachineFunction *MF;
const TargetInstrInfo *TII;
const MachineLoopInfo *MLI;
const MachineDominatorTree *MDT;
MachineSchedulerPass();
MachineScheduler();
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
@ -56,11 +56,11 @@ public:
};
} // namespace
char MachineSchedulerPass::ID = 0;
char MachineScheduler::ID = 0;
char &llvm::MachineSchedulerPassID = MachineSchedulerPass::ID;
char &llvm::MachineSchedulerID = MachineScheduler::ID;
INITIALIZE_PASS_BEGIN(MachineSchedulerPass, "misched",
INITIALIZE_PASS_BEGIN(MachineScheduler, "misched",
"Machine Instruction Scheduler", false, false)
INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
@ -68,15 +68,15 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
INITIALIZE_PASS_END(MachineSchedulerPass, "misched",
INITIALIZE_PASS_END(MachineScheduler, "misched",
"Machine Instruction Scheduler", false, false)
MachineSchedulerPass::MachineSchedulerPass()
MachineScheduler::MachineScheduler()
: MachineFunctionPass(ID), MF(0), MLI(0), MDT(0) {
initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
}
void MachineSchedulerPass::getAnalysisUsage(AnalysisUsage &AU) const {
void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequiredID(MachineDominatorsID);
AU.addRequired<MachineLoopInfo>();
@ -102,7 +102,7 @@ namespace {
/// schedulers.
class MachineSchedRegistry : public MachinePassRegistryNode {
public:
typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedulerPass *);
typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineScheduler *);
// RegisterPassParser requires a (misnamed) FunctionPassCtor type.
typedef ScheduleDAGCtor FunctionPassCtor;
@ -137,7 +137,7 @@ public:
MachinePassRegistry MachineSchedRegistry::Registry;
static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P);
static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P);
/// MachineSchedOpt allows command line selection of the scheduler.
static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
@ -147,45 +147,22 @@ MachineSchedOpt("misched",
cl::desc("Machine instruction scheduler to use"));
//===----------------------------------------------------------------------===//
// Machine Instruction Scheduling Implementation
// Machine Instruction Scheduling Common Implementation
//===----------------------------------------------------------------------===//
namespace {
/// MachineScheduler is an implementation of ScheduleDAGInstrs that schedules
/// machine instructions while updating LiveIntervals.
class MachineScheduler : public ScheduleDAGInstrs {
MachineSchedulerPass *Pass;
class ScheduleTopDownLive : public ScheduleDAGInstrs {
protected:
MachineScheduler *Pass;
public:
MachineScheduler(MachineSchedulerPass *P):
ScheduleTopDownLive(MachineScheduler *P):
ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
virtual void Schedule();
};
} // namespace
static ScheduleDAGInstrs *createDefaultMachineSched(MachineSchedulerPass *P) {
return new MachineScheduler(P);
}
static MachineSchedRegistry
SchedDefaultRegistry("default", "Activate the scheduler pass, "
"but don't reorder instructions",
createDefaultMachineSched);
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
void MachineScheduler::Schedule() {
BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
SUnits[su].dumpAll(this));
// TODO: Put interesting things here.
}
bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
// Initialize the context of the pass.
MF = &mf;
MLI = &getAnalysis<MachineLoopInfo>();
@ -241,10 +218,45 @@ bool MachineSchedulerPass::runOnMachineFunction(MachineFunction &mf) {
return true;
}
void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
void MachineScheduler::print(raw_ostream &O, const Module* m) const {
// unimplemented
}
//===----------------------------------------------------------------------===//
// Placeholder for extending the machine instruction scheduler.
//===----------------------------------------------------------------------===//
namespace {
class DefaultMachineScheduler : public ScheduleTopDownLive {
public:
DefaultMachineScheduler(MachineScheduler *P):
ScheduleTopDownLive(P) {}
void Schedule();
};
} // namespace
static ScheduleDAGInstrs *createDefaultMachineSched(MachineScheduler *P) {
return new DefaultMachineScheduler(P);
}
static MachineSchedRegistry
SchedDefaultRegistry("default", "Activate the scheduler pass, "
"but don't reorder instructions",
createDefaultMachineSched);
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
void DefaultMachineScheduler::Schedule() {
BuildSchedGraph(&Pass->getAnalysis<AliasAnalysis>());
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
SUnits[su].dumpAll(this));
// TODO: Put interesting things here.
}
//===----------------------------------------------------------------------===//
// Machine Instruction Shuffler for Correctness Testing
//===----------------------------------------------------------------------===//
@ -252,11 +264,11 @@ void MachineSchedulerPass::print(raw_ostream &O, const Module* m) const {
#ifndef NDEBUG
namespace {
/// Reorder instructions as much as possible.
class InstructionShuffler : public ScheduleDAGInstrs {
MachineSchedulerPass *Pass;
class InstructionShuffler : public ScheduleTopDownLive {
MachineScheduler *Pass;
public:
InstructionShuffler(MachineSchedulerPass *P):
ScheduleDAGInstrs(*P->MF, *P->MLI, *P->MDT, /*IsPostRA=*/false), Pass(P) {}
InstructionShuffler(MachineScheduler *P):
ScheduleTopDownLive(P) {}
/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
/// time to do some work.
@ -266,7 +278,7 @@ public:
};
} // namespace
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedulerPass *P) {
static ScheduleDAGInstrs *createInstructionShuffler(MachineScheduler *P) {
return new InstructionShuffler(P);
}
static MachineSchedRegistry ShufflerRegistry("shuffle",

2
llvm/lib/CodeGen/RegAllocBasic.cpp
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@ -129,7 +129,7 @@ RABasic::RABasic(): MachineFunctionPass(ID) {
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());

4
llvm/lib/CodeGen/RegAllocGreedy.cpp
View File

@ -316,7 +316,7 @@ RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPassPass(*PassRegistry::getPassRegistry());
initializeMachineSchedulerPass(*PassRegistry::getPassRegistry());
initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
@ -339,7 +339,7 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequiredID(StrongPHIEliminationID);
AU.addRequiredTransitiveID(RegisterCoalescerPassID);
if (EnableMachineSched)
AU.addRequiredID(MachineSchedulerPassID);
AU.addRequiredID(MachineSchedulerID);
AU.addRequired<CalculateSpillWeights>();
AU.addRequired<LiveStacks>();
AU.addPreserved<LiveStacks>();