From e0c5bff720b2ad211c7cffa91be14b64618e69eb Mon Sep 17 00:00:00 2001
From: Venkatraman Govindaraju <venkatra@cs.wisc.edu>
Date: Sat, 1 Mar 2014 18:54:52 +0000
Subject: [PATCH] [Sparc] Add support for parsing sparcv9 instructions
 addc/subc/addccc/subccc.

llvm-svn: 202598
---
 .../Target/Sparc/AsmParser/SparcAsmParser.cpp |  8 ++-----
 .../Sparc/MCTargetDesc/SparcMCTargetDesc.cpp  |  3 +++
 llvm/lib/Target/Sparc/SparcInstrAliases.td    |  6 +++++
 llvm/lib/Target/Sparc/SparcInstrInfo.td       |  3 ++-
 llvm/test/MC/Sparc/sparcv9-instructions.s     | 23 +++++++++++++++++++
 5 files changed, 36 insertions(+), 7 deletions(-)
 create mode 100644 llvm/test/MC/Sparc/sparcv9-instructions.s

diff --git a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
index 62d9ca0d2ad7..d00456e99902 100644
--- a/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
+++ b/llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp
@@ -419,7 +419,7 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return Error(ErrorLoc, "invalid operand for instruction");
   }
   case Match_MnemonicFail:
-    return Error(IDLoc, "invalid instruction");
+    return Error(IDLoc, "invalid instruction mnemonic");
   }
   return true;
 }
@@ -448,11 +448,7 @@ ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                  SMLoc NameLoc,
                  SmallVectorImpl<MCParsedAsmOperand*> &Operands)
 {
-  // Check if we have valid mnemonic.
-  if (!mnemonicIsValid(Name, 0)) {
-    Parser.eatToEndOfStatement();
-    return Error(NameLoc, "Unknown instruction");
-  }
+
   // First operand in MCInst is instruction mnemonic.
   Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
 
diff --git a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
index 1e6d20460010..1961254e48a9 100644
--- a/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
+++ b/llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
@@ -67,6 +67,9 @@ static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) {
 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
                                                    StringRef FS) {
   MCSubtargetInfo *X = new MCSubtargetInfo();
+  Triple TheTriple(TT);
+  if (CPU.empty())
+    CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8";
   InitSparcMCSubtargetInfo(X, TT, CPU, FS);
   return X;
 }
diff --git a/llvm/lib/Target/Sparc/SparcInstrAliases.td b/llvm/lib/Target/Sparc/SparcInstrAliases.td
index efa792438473..624a5a3de8cf 100644
--- a/llvm/lib/Target/Sparc/SparcInstrAliases.td
+++ b/llvm/lib/Target/Sparc/SparcInstrAliases.td
@@ -143,3 +143,9 @@ def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
 
 // restore -> restore %g0, %g0, %g0
 def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
+
+def : MnemonicAlias<"addc", "addx">, Requires<[HasV9]>;
+def : MnemonicAlias<"addccc", "addxcc">, Requires<[HasV9]>;
+
+def : MnemonicAlias<"subc", "subx">, Requires<[HasV9]>;
+def : MnemonicAlias<"subccc", "subxcc">, Requires<[HasV9]>;
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td
index d8555038706e..9bf7be9e8f77 100644
--- a/llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -29,7 +29,8 @@ def Is64Bit : Predicate<"Subtarget.is64Bit()">;
 
 // HasV9 - This predicate is true when the target processor supports V9
 // instructions.  Note that the machine may be running in 32-bit mode.
-def HasV9   : Predicate<"Subtarget.isV9()">;
+def HasV9   : Predicate<"Subtarget.isV9()">,
+              AssemblerPredicate<"FeatureV9">;
 
 // HasNoV9 - This predicate is true when the target doesn't have V9
 // instructions.  Use of this is just a hack for the isel not having proper
diff --git a/llvm/test/MC/Sparc/sparcv9-instructions.s b/llvm/test/MC/Sparc/sparcv9-instructions.s
new file mode 100644
index 000000000000..37f4c8b2f6b9
--- /dev/null
+++ b/llvm/test/MC/Sparc/sparcv9-instructions.s
@@ -0,0 +1,23 @@
+! RUN: not llvm-mc %s -arch=sparc   -show-encoding 2>&1 | FileCheck %s --check-prefix=V8
+! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s --check-prefix=V9
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: addc %g2, %g1, %g3
+        ! V9:      addx %g2, %g1, %g3              ! encoding: [0x86,0x40,0x80,0x01]
+        addc %g2, %g1, %g3
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: addccc %g1, %g2, %g3
+        ! V9:      addxcc %g1, %g2, %g3            ! encoding: [0x86,0xc0,0x40,0x02]
+        addccc %g1, %g2, %g3
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: subc %g2, %g1, %g3
+        ! V9:      subx %g2, %g1, %g3          ! encoding: [0x86,0x60,0x80,0x01]
+        subc %g2, %g1, %g3
+
+        ! V8:      error: invalid instruction mnemonic
+        ! V8-NEXT: subccc %g1, %g2, %g3
+        ! V9:      subxcc %g1, %g2, %g3         ! encoding: [0x86,0xe0,0x40,0x02]
+        subccc %g1, %g2, %g3
+