From e0ad108f044ef021bc6503fc40325ccee12c5dbf Mon Sep 17 00:00:00 2001
From: Anton Korobeynikov <asl@math.spbu.ru>
Date: Thu, 16 Jul 2009 14:14:54 +0000
Subject: [PATCH] Remove redundand register move

llvm-svn: 76004
---
 .../Target/SystemZ/SystemZISelDAGToDAG.cpp    | 28 +++++--------------
 llvm/lib/Target/SystemZ/SystemZInstrInfo.td   |  8 ++++++
 2 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 3df814e1bb0b..c63376683a6e 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -645,7 +645,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
       default: assert(0 && "Unsupported VT!");
       case MVT::i32:
         Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
-        ClrOpc = SystemZ::MOV32ri16;
+        ClrOpc = SystemZ::MOV64Pr0_even;
         ResVT = MVT::v2i32;
         break;
       case MVT::i64:
@@ -669,15 +669,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
                             CurDAG->getTargetConstant(subreg_odd, MVT::i32));
 
     // Zero out even subreg, if needed
-    if (ClrOpc) {
-      SDNode * ZeroHi = CurDAG->getTargetNode(SystemZ::MOV32ri16, dl, NVT,
-                                        CurDAG->getTargetConstant(0, MVT::i32));
-      Dividend =
-        CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
-                              SDValue(Dividend, 0),
-                              SDValue(ZeroHi, 0),
-                              CurDAG->getTargetConstant(subreg_even, MVT::i32));
-    }
+    if (ClrOpc)
+      Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
 
     SDNode *Result;
     SDValue DivVal = SDValue(Dividend, 0);
@@ -736,12 +729,12 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
       default: assert(0 && "Unsupported VT!");
       case MVT::i32:
         Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
-        ClrOpc = SystemZ::MOV32ri16;
+        ClrOpc = SystemZ::MOV64Pr0_even;
         ResVT = MVT::v2i32;
         break;
       case MVT::i64:
         Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
-        ClrOpc = SystemZ::MOV64ri16;
+        ClrOpc = SystemZ::MOV128r0_even;
         ResVT = MVT::v2i64;
         break;
     }
@@ -760,15 +753,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
                             SDValue(Tmp, 0), SDValue(Dividend, 0),
                             CurDAG->getTargetConstant(subreg_odd, MVT::i32));
 
-    // Zero out even subreg, if needed
-    SDNode * ZeroHi = CurDAG->getTargetNode(ClrOpc, dl, NVT,
-                                            CurDAG->getTargetConstant(0,
-                                                                      MVT::i32));
-    Dividend =
-      CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
-                            SDValue(Dividend, 0),
-                            SDValue(ZeroHi, 0),
-                            CurDAG->getTargetConstant(subreg_even, MVT::i32));
+    // Zero out even subreg
+    Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
 
     SDValue DivVal = SDValue(Dividend, 0);
     SDNode *Result;
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 5a34d95e6717..a1202aa2e1af 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -370,6 +370,14 @@ def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
                        "lmg\t{$from, $to, $dst}",
                        []>;
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
+def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
+                           "lhi\t${dst:subreg_even}, 0",
+                           []>;
+def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
+                           "lghi\t${dst:subreg_even}, 0",
+                           []>;
+}
 
 //===----------------------------------------------------------------------===//
 // Arithmetic Instructions