[Hexagon] Recognize "q" and "v" in inline-asm as register constraints

Clang follow-up to r269933.

llvm-svn: 269934

clang/lib/Basic/Targets.cpp

@@ -6016,7 +6016,16 @@ public:
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override {
-    return true;
+    switch (*Name) {
+      case 'v':
+      case 'q':
+        if (HasHVX) {
+          Info.setAllowsRegister();
+          return true;
+        }
+        break;
+    }
+    return false;
   }
 
   void getTargetDefines(const LangOptions &Opts,

clang/test/CodeGen/hexagon-inline-asm.c

@@ -0,0 +1,11 @@
+// RUN: %clang_cc1 -triple hexagon-unknown-elf -target-feature +hvx -emit-llvm -o - %s | FileCheck %s
+
+typedef int v64 __attribute__((__vector_size__(64)))
+    __attribute__((aligned(64)));
+
+void foo(v64 v0, v64 v1, v64 *p) {
+  v64 q0;
+  asm ("%0 = vgtw(%1.w,%2.w)" : "=q"(q0) : "v"(v0), "v"(v1));
+// CHECK: call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32>{{.*}}, <16 x i32>{{.*}})
+  *p = q0;
+}