diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
index 8acce42d4c43..360f7db3e562 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -290,15 +290,15 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
                                       VSPLT_shuffle_mask:$UIMM))]>;
 
-def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
-                      "vspltisb $vD, $SIMM", VecPerm,
-                      [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
-def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
-                      "vspltish $vD, $SIMM", VecPerm,
-                      [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
-def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
-                      "vspltisw $vD, $SIMM", VecPerm,
-                      [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
+def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
+                       "vspltisb $vD, $SIMM", VecPerm,
+                       [(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
+def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
+                       "vspltish $vD, $SIMM", VecPerm,
+                       [(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
+def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
+                       "vspltisw $vD, $SIMM", VecPerm,
+                       [(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
 
 
 // Altivec Comparisons.
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 7319463a73fb..9f87b278e674 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -663,6 +663,21 @@ class VXForm_2<bits<11> xo, dag OL, string asmstr,
   let Inst{21-31} = xo;
 }
 
+class VXForm_3<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> IMM;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = IMM;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+
 // E-4 VXR-Form
 class VXRForm_1<bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>