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Implement a DAGCombine in MipsISelLowering.cpp which transforms the following 

pattern:

(add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))

"tjt" is a TargetJumpTable node. 

llvm-svn: 158419
This commit is contained in:
Akira Hatanaka 2012-06-13 20:33:18 +00:00
parent 8acadcb84b
commit df5205ef3d
3 changed files with 46 additions and 17 deletions
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8
llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp
View File

@ -335,11 +335,11 @@ SelectAddr(SDNode *Parent, SDValue Addr, SDValue &Base, SDValue &Offset) {
// lui $2, %hi($CPI1_0)
// lwc1 $f0, %lo($CPI1_0)($2)
if (Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
SDValue LoVal = Addr.getOperand(1);
if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
SDValue LoVal = Addr.getOperand(1), Opnd0 = LoVal.getOperand(0);
if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
isa<JumpTableSDNode>(Opnd0)) {
Base = Addr.getOperand(0);
Offset = LoVal.getOperand(0);
Offset = Opnd0;
return true;
}
}

30
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -295,6 +295,7 @@ MipsTargetLowering(MipsTargetMachine &TM)
setTargetDAGCombine(ISD::SELECT);
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::ADD);
setMinFunctionAlignment(HasMips64 ? 3 : 2);
@ -733,6 +734,33 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
DAG.getConstant(SMSize0, MVT::i32), And0.getOperand(0));
}
static SDValue PerformADDCombine(SDNode *N, SelectionDAG& DAG,
TargetLowering::DAGCombinerInfo &DCI,
const MipsSubtarget* Subtarget) {
// (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
if (DCI.isBeforeLegalizeOps())
return SDValue();
SDValue Add = N->getOperand(1);
if (Add.getOpcode() != ISD::ADD)
return SDValue();
SDValue Lo = Add.getOperand(1);
if ((Lo.getOpcode() != MipsISD::Lo) ||
(Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
return SDValue();
EVT ValTy = N->getValueType(0);
DebugLoc DL = N->getDebugLoc();
SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
Add.getOperand(0));
return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
}
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
const {
SelectionDAG &DAG = DCI.DAG;
@ -753,6 +781,8 @@ SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
return PerformANDCombine(N, DAG, DCI, Subtarget);
case ISD::OR:
return PerformORCombine(N, DAG, DCI, Subtarget);
case ISD::ADD:
return PerformADDCombine(N, DAG, DCI, Subtarget);
}
return SDValue();

25
llvm/test/CodeGen/Mips/2010-07-20-Switch.ll
View File

@ -7,21 +7,20 @@ entry:
%x = alloca i32, align 4 ; <i32*> [#uses=2]
store volatile i32 2, i32* %x, align 4
%0 = load volatile i32* %x, align 4 ; <i32> [#uses=1]
; STATIC-O32: lui $[[R0:[0-9]+]], %hi($JTI0_0)
; STATIC-O32: addiu ${{[0-9]+}}, $[[R0]], %lo($JTI0_0)
; STATIC-O32: sll ${{[0-9]+}}, ${{[0-9]+}}, 2
; PIC-O32: lw $[[R0:[0-9]+]], %got($JTI0_0)
; PIC-O32: addiu $[[R1:[0-9]+]], $[[R0]], %lo($JTI0_0)
; PIC-O32: sll $[[R2:[0-9]+]], ${{[0-9]+}}, 2
; PIC-O32: addu $[[R3:[0-9]+]], $[[R2]], $[[R1]]
; PIC-O32: lw $[[R4:[0-9]+]], 0($[[R3]])
; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0)
; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]])
; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0)
; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
; PIC-O32: jr $[[R5]]
; PIC-N64: ld $[[R0:[0-9]+]], %got_page($JTI0_0)
; PIC-N64: daddiu $[[R1:[0-9]+]], $[[R0]], %got_ofst($JTI0_0)
; PIC-N64: dsll $[[R2:[0-9]+]], ${{[0-9]+}}, 3
; PIC-N64: daddu $[[R3:[0-9]+]], $[[R2:[0-9]+]], $[[R1]]
; PIC-N64: ld $[[R4:[0-9]+]], 0($[[R3]])
; PIC-N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 3
; PIC-N64: ld $[[R1:[0-9]+]], %got_page($JTI0_0)
; PIC-N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst($JTI0_0)($[[R2]])
; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
; PIC-N64: jr $[[R5]]
switch i32 %0, label %bb4 [