Handle a special case xor undef, undef -> 0. Technically this should be transformed to undef. But this is such a common idiom (misuse) we are going to handle it.
llvm-svn: 48792
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@ -2119,6 +2119,9 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
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if (FoldedVOp.Val) return FoldedVOp;
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if (FoldedVOp.Val) return FoldedVOp;
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}
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}
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// fold (xor undef, undef) -> 0. This is a common idiom (misuse).
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if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
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return DAG.getConstant(0, VT);
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// fold (xor x, undef) -> undef
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// fold (xor x, undef) -> undef
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if (N0.getOpcode() == ISD::UNDEF)
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if (N0.getOpcode() == ISD::UNDEF)
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return N0;
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return N0;
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@ -2245,6 +2245,12 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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// Fold a bunch of operators when the RHS is undef.
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// Fold a bunch of operators when the RHS is undef.
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if (N2.getOpcode() == ISD::UNDEF) {
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if (N2.getOpcode() == ISD::UNDEF) {
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switch (Opcode) {
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switch (Opcode) {
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case ISD::XOR:
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if (N1.getOpcode() == ISD::UNDEF)
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// Handle undef ^ undef -> 0 special case. This is a common
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// idiom (misuse).
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return getConstant(0, VT);
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// fallthrough
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case ISD::ADD:
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case ISD::ADD:
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case ISD::ADDC:
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case ISD::ADDC:
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case ISD::ADDE:
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case ISD::ADDE:
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@ -2258,7 +2264,6 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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case ISD::SDIV:
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case ISD::SDIV:
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case ISD::UREM:
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case ISD::UREM:
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case ISD::SREM:
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case ISD::SREM:
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case ISD::XOR:
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return N2; // fold op(arg1, undef) -> undef
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return N2; // fold op(arg1, undef) -> undef
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case ISD::MUL:
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case ISD::MUL:
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case ISD::AND:
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case ISD::AND:
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@ -474,9 +474,14 @@ Constant *llvm::ConstantFoldBinaryInstruction(unsigned Opcode,
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// Handle UndefValue up front
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// Handle UndefValue up front
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if (isa<UndefValue>(C1) || isa<UndefValue>(C2)) {
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if (isa<UndefValue>(C1) || isa<UndefValue>(C2)) {
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switch (Opcode) {
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switch (Opcode) {
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case Instruction::Xor:
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if (isa<UndefValue>(C1) && isa<UndefValue>(C2))
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// Handle undef ^ undef -> 0 special case. This is a common
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// idiom (misuse).
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return Constant::getNullValue(C1->getType());
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// Fallthrough
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case Instruction::Add:
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case Instruction::Add:
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case Instruction::Sub:
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case Instruction::Sub:
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case Instruction::Xor:
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return UndefValue::get(C1->getType());
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return UndefValue::get(C1->getType());
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case Instruction::Mul:
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case Instruction::Mul:
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case Instruction::And:
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case Instruction::And:
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@ -0,0 +1,11 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep xor | count 2
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define <4 x i32> @t1() {
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%tmp = xor <4 x i32> undef, undef
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ret <4 x i32> %tmp
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}
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define i32 @t2() {
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%tmp = xor i32 undef, undef
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ret i32 %tmp
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}
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