[MIR] Add simple PRE pass to MachineCSE
This is the second part of the commit fixing PR38917 (hoisting partitially redundant machine instruction). Most of PRE (partitial redundancy elimination) and CSE work is done on LLVM IR, but some of redundancy arises during DAG legalization. Machine CSE is not enough to deal with it. This simple PRE implementation works a little bit intricately: it passes before CSE, looking for partitial redundancy and transforming it to fully redundancy, anticipating that the next CSE step will eliminate this created redundancy. If CSE doesn't eliminate this, than created instruction will remain dead and eliminated later by Remove Dead Machine Instructions pass. The third part of the commit is supposed to refactor MachineCSE, to make it more clear and to merge MachinePRE with MachineCSE, so one need no rely on further Remove Dead pass to clear instrs not eliminated by CSE. First step: https://reviews.llvm.org/D54839 Fixes llvm.org/PR38917 llvm-svn: 361356
This commit is contained in:
Anton Afanasyev
parent
1c61471ab1
commit
df00c6a54f
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@ -19,6 +19,7 @@
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/CFG.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -49,6 +50,8 @@ using namespace llvm;
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STATISTIC(NumCoalesces, "Number of copies coalesced");
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STATISTIC(NumCSEs, "Number of common subexpression eliminated");
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STATISTIC(NumPREs, "Number of partial redundant expression"
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" transformed to fully redundant");
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STATISTIC(NumPhysCSEs,
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"Number of physreg referencing common subexpr eliminated");
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STATISTIC(NumCrossBBCSEs,
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@ -84,6 +87,7 @@ namespace {
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void releaseMemory() override {
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ScopeMap.clear();
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PREMap.clear();
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Exps.clear();
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}
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@ -98,6 +102,7 @@ namespace {
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unsigned LookAheadLimit = 0;
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DenseMap<MachineBasicBlock *, ScopeType *> ScopeMap;
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DenseMap<MachineInstr *, MachineBasicBlock *, MachineInstrExpressionTrait> PREMap;
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ScopedHTType VNT;
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SmallVector<MachineInstr *, 64> Exps;
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unsigned CurrVN = 0;
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@ -116,13 +121,17 @@ namespace {
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PhysDefVector &PhysDefs, bool &NonLocal) const;
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bool isCSECandidate(MachineInstr *MI);
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bool isProfitableToCSE(unsigned CSReg, unsigned Reg,
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MachineInstr *CSMI, MachineInstr *MI);
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MachineBasicBlock *CSBB, MachineInstr *MI);
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void EnterScope(MachineBasicBlock *MBB);
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void ExitScope(MachineBasicBlock *MBB);
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bool ProcessBlock(MachineBasicBlock *MBB);
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bool ProcessBlockCSE(MachineBasicBlock *MBB);
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void ExitScopeIfDone(MachineDomTreeNode *Node,
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DenseMap<MachineDomTreeNode*, unsigned> &OpenChildren);
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bool PerformCSE(MachineDomTreeNode *Node);
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bool isPRECandidate(MachineInstr *MI);
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bool ProcessBlockPRE(MachineDominatorTree *MDT, MachineBasicBlock *MBB);
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bool PerformSimplePRE(MachineDominatorTree *DT);
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};
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} // end anonymous namespace
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@ -405,9 +414,10 @@ bool MachineCSE::isCSECandidate(MachineInstr *MI) {
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}
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/// isProfitableToCSE - Return true if it's profitable to eliminate MI with a
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/// common expression that defines Reg.
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/// common expression that defines Reg. CSBB is basic block where CSReg is
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/// defined.
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bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
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MachineInstr *CSMI, MachineInstr *MI) {
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MachineBasicBlock *CSBB, MachineInstr *MI) {
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// FIXME: Heuristics that works around the lack the live range splitting.
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// If CSReg is used at all uses of Reg, CSE should not increase register
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@ -433,7 +443,6 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
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// an immediate predecessor. We don't want to increase register pressure and
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// end up causing other computation to be spilled.
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if (TII->isAsCheapAsAMove(*MI)) {
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MachineBasicBlock *CSBB = CSMI->getParent();
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MachineBasicBlock *BB = MI->getParent();
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if (CSBB != BB && !CSBB->isSuccessor(BB))
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return false;
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@ -488,7 +497,7 @@ void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
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ScopeMap.erase(SI);
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}
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bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) {
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bool Changed = false;
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SmallVector<std::pair<unsigned, unsigned>, 8> CSEPairs;
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@ -598,7 +607,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
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TargetRegisterInfo::isVirtualRegister(NewReg) &&
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"Do not CSE physical register defs!");
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if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
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if (!isProfitableToCSE(NewReg, OldReg, CSMI->getParent(), MI)) {
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LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
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DoCSE = false;
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break;
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@ -738,7 +747,7 @@ bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
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for (MachineDomTreeNode *Node : Scopes) {
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MachineBasicBlock *MBB = Node->getBlock();
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EnterScope(MBB);
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Changed |= ProcessBlock(MBB);
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Changed |= ProcessBlockCSE(MBB);
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// If it's a leaf node, it's done. Traverse upwards to pop ancestors.
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ExitScopeIfDone(Node, OpenChildren);
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}
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@ -746,6 +755,98 @@ bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
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return Changed;
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}
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// We use stronger checks for PRE candidate rather than for CSE ones to embrace
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// checks inside ProcessBlockCSE(), not only inside isCSECandidate(). This helps
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// to exclude instrs created by PRE that won't be CSEed later.
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bool MachineCSE::isPRECandidate(MachineInstr *MI) {
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if (!isCSECandidate(MI) ||
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MI->isNotDuplicable() ||
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MI->isAsCheapAsAMove() ||
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MI->getNumDefs() != 1 ||
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MI->getNumExplicitDefs() != 1)
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return false;
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for (auto def: MI->defs())
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if (!TRI->isVirtualRegister(def.getReg()))
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return false;
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for (auto use: MI->uses())
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if (use.isReg() && !TRI->isVirtualRegister(use.getReg()))
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return false;
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return true;
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}
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bool MachineCSE::ProcessBlockPRE(MachineDominatorTree *DT, MachineBasicBlock *MBB) {
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bool Changed = false;
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
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MachineInstr *MI = &*I;
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++I;
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if (!isPRECandidate(MI))
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continue;
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if (!PREMap.count(MI)) {
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PREMap[MI] = MBB;
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continue;
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}
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auto MBB1 = PREMap[MI];
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assert(!DT->properlyDominates(MBB, MBB1) &&
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"MBB cannot properly dominate MBB1 while DFS through dominators tree!");
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auto CMBB = DT->findNearestCommonDominator(MBB, MBB1);
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// Two instrs are partial redundant if their basic blocks are reachable
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// from one to another but one doesn't dominate another.
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if (CMBB != MBB1) {
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auto BB = MBB->getBasicBlock(), BB1 = MBB1->getBasicBlock();
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if (BB != nullptr && BB1 != nullptr &&
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(isPotentiallyReachable(BB1, BB) ||
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isPotentiallyReachable(BB, BB1))) {
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assert(MI->getOperand(0).isDef() &&
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"First operand of instr with one explicit def must be this def");
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unsigned VReg = MI->getOperand(0).getReg();
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unsigned NewReg = MRI->cloneVirtualRegister(VReg);
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if (!isProfitableToCSE(NewReg, VReg, CMBB, MI))
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continue;
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MachineInstr &NewMI = TII->duplicate(*CMBB, CMBB->getFirstTerminator(), *MI);
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NewMI.getOperand(0).setReg(NewReg);
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PREMap[MI] = CMBB;
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++NumPREs;
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Changed = true;
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}
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}
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}
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return Changed;
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}
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// This simple PRE (partial redundancy elimination) pass doesn't actually
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// eliminate partial redundancy but transforms it to full redundancy,
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// anticipating that the next CSE step will eliminate this created redundancy.
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// If CSE doesn't eliminate this, than created instruction will remain dead
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// and eliminated later by Remove Dead Machine Instructions pass.
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bool MachineCSE::PerformSimplePRE(MachineDominatorTree *DT) {
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SmallVector<MachineDomTreeNode*, 32> BBs;
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PREMap.clear();
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bool Changed = false;
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BBs.push_back(DT->getRootNode());
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do {
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auto Node = BBs.pop_back_val();
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (MachineDomTreeNode *Child : Children)
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BBs.push_back(Child);
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MachineBasicBlock *MBB = Node->getBlock();
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Changed |= ProcessBlockPRE(DT, MBB);
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} while (!BBs.empty());
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return Changed;
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}
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bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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@ -756,5 +857,8 @@ bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
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AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
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DT = &getAnalysis<MachineDominatorTree>();
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LookAheadLimit = TII->getMachineCSELookAheadLimit();
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return PerformCSE(DT->getRootNode());
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bool ChangedPRE, ChangedCSE;
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ChangedPRE = PerformSimplePRE(DT);
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ChangedCSE = PerformCSE(DT->getRootNode());
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return ChangedPRE || ChangedCSE;
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}
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@ -27,8 +27,7 @@ if.then: ; preds = %entry
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if.end: ; preds = %entry, %if.then
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; CHECK: lw $[[R2:[0-9]+]], %got(sf2)
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; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
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; CHECK: lw $[[R3:[0-9]+]], %got(caller.sf1)
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; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R3]])
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; CHECK: sw ${{[0-9]+}}, %lo(caller.sf1)($[[R1]])
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%tobool3 = icmp ne i32 %a0, 0
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%tmp4 = load void (...)*, void (...)** @gf1, align 4
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%cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*)
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@ -236,18 +236,17 @@ define <4 x i32> @masked_gather_v4i32(<4 x i32*> %ptrs, <4 x i1> %masks, <4 x i3
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; NOGATHER-NEXT: vpinsrd $1, (%rax), %xmm2, %xmm2
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; NOGATHER-NEXT: .LBB4_4: # %else2
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; NOGATHER-NEXT: vpextrb $8, %xmm1, %eax
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; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB4_6
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; NOGATHER-NEXT: # %bb.5: # %cond.load4
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; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm3
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; NOGATHER-NEXT: vmovq %xmm3, %rax
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; NOGATHER-NEXT: vmovq %xmm0, %rax
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; NOGATHER-NEXT: vpinsrd $2, (%rax), %xmm2, %xmm2
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; NOGATHER-NEXT: .LBB4_6: # %else5
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; NOGATHER-NEXT: vpextrb $12, %xmm1, %eax
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB4_8
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; NOGATHER-NEXT: # %bb.7: # %cond.load7
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; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0
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; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax
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; NOGATHER-NEXT: vpinsrd $3, (%rax), %xmm2, %xmm2
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; NOGATHER-NEXT: .LBB4_8: # %else8
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@ -295,18 +294,17 @@ define <4 x float> @masked_gather_v4float(<4 x float*> %ptrs, <4 x i1> %masks, <
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; NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0],mem[0],xmm2[2,3]
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; NOGATHER-NEXT: .LBB5_4: # %else2
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; NOGATHER-NEXT: vpextrb $8, %xmm1, %eax
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; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB5_6
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; NOGATHER-NEXT: # %bb.5: # %cond.load4
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; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm3
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; NOGATHER-NEXT: vmovq %xmm3, %rax
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; NOGATHER-NEXT: vmovq %xmm0, %rax
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; NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
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; NOGATHER-NEXT: .LBB5_6: # %else5
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; NOGATHER-NEXT: vpextrb $12, %xmm1, %eax
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB5_8
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; NOGATHER-NEXT: # %bb.7: # %cond.load7
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; NOGATHER-NEXT: vextractf128 $1, %ymm0, %xmm0
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; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax
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; NOGATHER-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
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; NOGATHER-NEXT: .LBB5_8: # %else8
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@ -366,11 +364,11 @@ define <8 x i32> @masked_gather_v8i32(<8 x i32*>* %ptr, <8 x i1> %masks, <8 x i3
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; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7]
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; NOGATHER-NEXT: .LBB6_4: # %else2
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; NOGATHER-NEXT: vpextrb $4, %xmm0, %eax
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; NOGATHER-NEXT: vextractf128 $1, %ymm3, %xmm3
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB6_6
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; NOGATHER-NEXT: # %bb.5: # %cond.load4
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; NOGATHER-NEXT: vextractf128 $1, %ymm3, %xmm4
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; NOGATHER-NEXT: vmovq %xmm4, %rax
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; NOGATHER-NEXT: vmovq %xmm3, %rax
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; NOGATHER-NEXT: vpinsrd $2, (%rax), %xmm1, %xmm4
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; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7]
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; NOGATHER-NEXT: .LBB6_6: # %else5
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@ -378,7 +376,6 @@ define <8 x i32> @masked_gather_v8i32(<8 x i32*>* %ptr, <8 x i1> %masks, <8 x i3
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB6_8
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; NOGATHER-NEXT: # %bb.7: # %cond.load7
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; NOGATHER-NEXT: vextractf128 $1, %ymm3, %xmm3
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; NOGATHER-NEXT: vpextrq $1, %xmm3, %rax
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; NOGATHER-NEXT: vpinsrd $3, (%rax), %xmm1, %xmm3
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; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
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@ -402,11 +399,11 @@ define <8 x i32> @masked_gather_v8i32(<8 x i32*>* %ptr, <8 x i1> %masks, <8 x i3
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; NOGATHER-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
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; NOGATHER-NEXT: .LBB6_12: # %else14
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; NOGATHER-NEXT: vpextrb $12, %xmm0, %eax
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; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm2
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB6_14
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; NOGATHER-NEXT: # %bb.13: # %cond.load16
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; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm3
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; NOGATHER-NEXT: vmovq %xmm3, %rax
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; NOGATHER-NEXT: vmovq %xmm2, %rax
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; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm3
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; NOGATHER-NEXT: vpinsrd $2, (%rax), %xmm3, %xmm3
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; NOGATHER-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
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@ -415,8 +412,7 @@ define <8 x i32> @masked_gather_v8i32(<8 x i32*>* %ptr, <8 x i1> %masks, <8 x i3
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB6_16
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; NOGATHER-NEXT: # %bb.15: # %cond.load19
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; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm0
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; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax
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; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax
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; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm0
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; NOGATHER-NEXT: vpinsrd $3, (%rax), %xmm0, %xmm0
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; NOGATHER-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
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@ -477,11 +473,11 @@ define <8 x float> @masked_gather_v8float(<8 x float*>* %ptr, <8 x i1> %masks, <
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; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7]
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; NOGATHER-NEXT: .LBB7_4: # %else2
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; NOGATHER-NEXT: vpextrb $4, %xmm0, %eax
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; NOGATHER-NEXT: vextractf128 $1, %ymm3, %xmm3
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB7_6
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; NOGATHER-NEXT: # %bb.5: # %cond.load4
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; NOGATHER-NEXT: vextractf128 $1, %ymm3, %xmm4
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; NOGATHER-NEXT: vmovq %xmm4, %rax
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; NOGATHER-NEXT: vmovq %xmm3, %rax
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; NOGATHER-NEXT: vinsertps {{.*#+}} xmm4 = xmm1[0,1],mem[0],xmm1[3]
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; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm4[0,1,2,3],ymm1[4,5,6,7]
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; NOGATHER-NEXT: .LBB7_6: # %else5
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@ -489,7 +485,6 @@ define <8 x float> @masked_gather_v8float(<8 x float*>* %ptr, <8 x i1> %masks, <
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; NOGATHER-NEXT: testb $1, %al
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; NOGATHER-NEXT: je .LBB7_8
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; NOGATHER-NEXT: # %bb.7: # %cond.load7
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm3, %xmm3
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm3, %rax
|
||||
; NOGATHER-NEXT: vinsertps {{.*#+}} xmm3 = xmm1[0,1,2],mem[0]
|
||||
; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
|
||||
|
|
@ -514,11 +509,11 @@ define <8 x float> @masked_gather_v8float(<8 x float*>* %ptr, <8 x i1> %masks, <
|
|||
; NOGATHER-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
|
||||
; NOGATHER-NEXT: .LBB7_12: # %else14
|
||||
; NOGATHER-NEXT: vpextrb $12, %xmm0, %eax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm2
|
||||
; NOGATHER-NEXT: testb $1, %al
|
||||
; NOGATHER-NEXT: je .LBB7_14
|
||||
; NOGATHER-NEXT: # %bb.13: # %cond.load16
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm3
|
||||
; NOGATHER-NEXT: vmovq %xmm3, %rax
|
||||
; NOGATHER-NEXT: vmovq %xmm2, %rax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; NOGATHER-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],mem[0],xmm3[3]
|
||||
; NOGATHER-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
|
||||
|
|
@ -527,8 +522,7 @@ define <8 x float> @masked_gather_v8float(<8 x float*>* %ptr, <8 x i1> %masks, <
|
|||
; NOGATHER-NEXT: testb $1, %al
|
||||
; NOGATHER-NEXT: je .LBB7_16
|
||||
; NOGATHER-NEXT: # %bb.15: # %cond.load19
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm0
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm0
|
||||
; NOGATHER-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
|
||||
; NOGATHER-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
|
||||
|
|
@ -583,11 +577,11 @@ define <4 x i64> @masked_gather_v4i64(<4 x i64*>* %ptr, <4 x i1> %masks, <4 x i6
|
|||
; NOGATHER-NEXT: vblendps {{.*#+}} ymm1 = ymm3[0,1,2,3],ymm1[4,5,6,7]
|
||||
; NOGATHER-NEXT: .LBB8_4: # %else2
|
||||
; NOGATHER-NEXT: vpextrb $8, %xmm0, %eax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm2
|
||||
; NOGATHER-NEXT: testb $1, %al
|
||||
; NOGATHER-NEXT: je .LBB8_6
|
||||
; NOGATHER-NEXT: # %bb.5: # %cond.load4
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm3
|
||||
; NOGATHER-NEXT: vmovq %xmm3, %rax
|
||||
; NOGATHER-NEXT: vmovq %xmm2, %rax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; NOGATHER-NEXT: vpinsrq $0, (%rax), %xmm3, %xmm3
|
||||
; NOGATHER-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
|
||||
|
|
@ -596,8 +590,7 @@ define <4 x i64> @masked_gather_v4i64(<4 x i64*>* %ptr, <4 x i1> %masks, <4 x i6
|
|||
; NOGATHER-NEXT: testb $1, %al
|
||||
; NOGATHER-NEXT: je .LBB8_8
|
||||
; NOGATHER-NEXT: # %bb.7: # %cond.load7
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm0
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm0
|
||||
; NOGATHER-NEXT: vpinsrq $1, (%rax), %xmm0, %xmm0
|
||||
; NOGATHER-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
|
||||
|
|
@ -652,11 +645,11 @@ define <4 x double> @masked_gather_v4double(<4 x double*>* %ptr, <4 x i1> %masks
|
|||
; NOGATHER-NEXT: vblendpd {{.*#+}} ymm1 = ymm3[0,1],ymm1[2,3]
|
||||
; NOGATHER-NEXT: .LBB9_4: # %else2
|
||||
; NOGATHER-NEXT: vpextrb $8, %xmm0, %eax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm2
|
||||
; NOGATHER-NEXT: testb $1, %al
|
||||
; NOGATHER-NEXT: je .LBB9_6
|
||||
; NOGATHER-NEXT: # %bb.5: # %cond.load4
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm3
|
||||
; NOGATHER-NEXT: vmovq %xmm3, %rax
|
||||
; NOGATHER-NEXT: vmovq %xmm2, %rax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm3
|
||||
; NOGATHER-NEXT: vmovlpd {{.*#+}} xmm3 = mem[0],xmm3[1]
|
||||
; NOGATHER-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
|
||||
|
|
@ -665,8 +658,7 @@ define <4 x double> @masked_gather_v4double(<4 x double*>* %ptr, <4 x i1> %masks
|
|||
; NOGATHER-NEXT: testb $1, %al
|
||||
; NOGATHER-NEXT: je .LBB9_8
|
||||
; NOGATHER-NEXT: # %bb.7: # %cond.load7
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm2, %xmm0
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; NOGATHER-NEXT: vpextrq $1, %xmm2, %rax
|
||||
; NOGATHER-NEXT: vextractf128 $1, %ymm1, %xmm0
|
||||
; NOGATHER-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
|
||||
; NOGATHER-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm1
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -70,17 +70,16 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
|
|||
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpextrb $8, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB0_6
|
||||
; AVX1-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; AVX1-NEXT: vmovq %xmm3, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||
; AVX1-NEXT: .LBB0_6: # %else5
|
||||
; AVX1-NEXT: vpextrb $12, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB0_8
|
||||
; AVX1-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||
; AVX1-NEXT: .LBB0_8: # %else8
|
||||
|
|
@ -111,17 +110,16 @@ define <4 x float> @gather_v4f32_ptr_v4i32(<4 x float*> %ptr, <4 x i32> %trigger
|
|||
; AVX2-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpextrb $8, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: je .LBB0_6
|
||||
; AVX2-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
|
||||
; AVX2-NEXT: vmovq %xmm3, %rax
|
||||
; AVX2-NEXT: vmovq %xmm0, %rax
|
||||
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||
; AVX2-NEXT: .LBB0_6: # %else5
|
||||
; AVX2-NEXT: vpextrb $12, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB0_8
|
||||
; AVX2-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||
; AVX2-NEXT: .LBB0_8: # %else8
|
||||
|
|
@ -227,17 +225,16 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
|
|||
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpextrb $8, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB1_6
|
||||
; AVX1-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; AVX1-NEXT: vmovq %xmm3, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||
; AVX1-NEXT: .LBB1_6: # %else5
|
||||
; AVX1-NEXT: vpextrb $12, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB1_8
|
||||
; AVX1-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||
; AVX1-NEXT: .LBB1_8: # %else8
|
||||
|
|
@ -273,17 +270,16 @@ define <4 x float> @gather_v4f32_v4i32_v4i32(float* %base, <4 x i32> %idx, <4 x
|
|||
; AVX2-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpextrb $8, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: je .LBB1_6
|
||||
; AVX2-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
|
||||
; AVX2-NEXT: vmovq %xmm3, %rax
|
||||
; AVX2-NEXT: vmovq %xmm0, %rax
|
||||
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||
; AVX2-NEXT: .LBB1_6: # %else5
|
||||
; AVX2-NEXT: vpextrb $12, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB1_8
|
||||
; AVX2-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||
; AVX2-NEXT: .LBB1_8: # %else8
|
||||
|
|
@ -388,17 +384,16 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
|
|||
; AVX1-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpextrb $8, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB2_6
|
||||
; AVX1-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; AVX1-NEXT: vmovq %xmm3, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||
; AVX1-NEXT: .LBB2_6: # %else5
|
||||
; AVX1-NEXT: vpextrb $12, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB2_8
|
||||
; AVX1-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||
; AVX1-NEXT: .LBB2_8: # %else8
|
||||
|
|
@ -433,17 +428,16 @@ define <4 x float> @gather_v4f32_v4i64_v4i32(float* %base, <4 x i64> %idx, <4 x
|
|||
; AVX2-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpextrb $8, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: je .LBB2_6
|
||||
; AVX2-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
|
||||
; AVX2-NEXT: vmovq %xmm3, %rax
|
||||
; AVX2-NEXT: vmovq %xmm0, %rax
|
||||
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],mem[0],xmm2[3]
|
||||
; AVX2-NEXT: .LBB2_6: # %else5
|
||||
; AVX2-NEXT: vpextrb $12, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB2_8
|
||||
; AVX2-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX2-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1,2],mem[0]
|
||||
; AVX2-NEXT: .LBB2_8: # %else8
|
||||
|
|
@ -662,15 +656,15 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: vpinsrb $1, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_4: # %else2
|
||||
; AVX1-NEXT: vpmovsxdq %xmm7, %xmm6
|
||||
; AVX1-NEXT: vpaddq %xmm5, %xmm4, %xmm8
|
||||
; AVX1-NEXT: vpaddq %xmm5, %xmm4, %xmm5
|
||||
; AVX1-NEXT: vpxor %xmm7, %xmm7, %xmm7
|
||||
; AVX1-NEXT: vpcmpeqb %xmm7, %xmm2, %xmm7
|
||||
; AVX1-NEXT: vpextrb $2, %xmm7, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB3_6
|
||||
; AVX1-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
|
||||
; AVX1-NEXT: vmovq %xmm5, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $2, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_6: # %else5
|
||||
; AVX1-NEXT: vpaddq %xmm6, %xmm4, %xmm6
|
||||
|
|
@ -678,11 +672,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB3_8
|
||||
; AVX1-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $3, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_8: # %else8
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm8, %ymm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm5, %ymm0
|
||||
; AVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5
|
||||
; AVX1-NEXT: vpcmpeqb %xmm5, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpextrb $4, %xmm5, %eax
|
||||
|
|
@ -702,15 +695,15 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: vpinsrb $5, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_12: # %else14
|
||||
; AVX1-NEXT: vpmovsxdq %xmm6, %xmm6
|
||||
; AVX1-NEXT: vpaddq %xmm7, %xmm4, %xmm8
|
||||
; AVX1-NEXT: vpaddq %xmm7, %xmm4, %xmm5
|
||||
; AVX1-NEXT: vpxor %xmm7, %xmm7, %xmm7
|
||||
; AVX1-NEXT: vpcmpeqb %xmm7, %xmm2, %xmm7
|
||||
; AVX1-NEXT: vpextrb $6, %xmm7, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB3_14
|
||||
; AVX1-NEXT: # %bb.13: # %cond.load16
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
|
||||
; AVX1-NEXT: vmovq %xmm5, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $6, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_14: # %else17
|
||||
; AVX1-NEXT: vpaddq %xmm6, %xmm4, %xmm6
|
||||
|
|
@ -718,12 +711,11 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB3_16
|
||||
; AVX1-NEXT: # %bb.15: # %cond.load19
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $7, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_16: # %else20
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm8, %ymm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm5, %ymm0
|
||||
; AVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5
|
||||
; AVX1-NEXT: vpcmpeqb %xmm5, %xmm2, %xmm5
|
||||
; AVX1-NEXT: vpextrb $8, %xmm5, %eax
|
||||
|
|
@ -748,10 +740,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: vpcmpeqb %xmm6, %xmm2, %xmm6
|
||||
; AVX1-NEXT: vpextrb $10, %xmm6, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB3_22
|
||||
; AVX1-NEXT: # %bb.21: # %cond.load28
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm7
|
||||
; AVX1-NEXT: vmovq %xmm7, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $10, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_22: # %else29
|
||||
; AVX1-NEXT: vpaddq %xmm5, %xmm4, %xmm4
|
||||
|
|
@ -759,7 +751,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB3_24
|
||||
; AVX1-NEXT: # %bb.23: # %cond.load31
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $11, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_24: # %else32
|
||||
|
|
@ -784,17 +775,16 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vpextrb $14, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: je .LBB3_30
|
||||
; AVX1-NEXT: # %bb.29: # %cond.load40
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vmovq %xmm2, %rax
|
||||
; AVX1-NEXT: vmovq %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $14, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_30: # %else41
|
||||
; AVX1-NEXT: vpextrb $15, %xmm1, %eax
|
||||
; AVX1-NEXT: testb $1, %al
|
||||
; AVX1-NEXT: je .LBB3_32
|
||||
; AVX1-NEXT: # %bb.31: # %cond.load43
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
|
||||
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX1-NEXT: vpinsrb $15, (%rax), %xmm3, %xmm3
|
||||
; AVX1-NEXT: .LBB3_32: # %else44
|
||||
|
|
@ -829,10 +819,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: vpcmpeqb %xmm6, %xmm2, %xmm6
|
||||
; AVX2-NEXT: vpextrb $2, %xmm6, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm5, %xmm5
|
||||
; AVX2-NEXT: je .LBB3_6
|
||||
; AVX2-NEXT: # %bb.5: # %cond.load4
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm5, %xmm7
|
||||
; AVX2-NEXT: vmovq %xmm7, %rax
|
||||
; AVX2-NEXT: vmovq %xmm5, %rax
|
||||
; AVX2-NEXT: vpinsrb $2, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_6: # %else5
|
||||
; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
|
||||
|
|
@ -840,7 +830,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB3_8
|
||||
; AVX2-NEXT: # %bb.7: # %cond.load7
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm5, %xmm5
|
||||
; AVX2-NEXT: vpextrq $1, %xmm5, %rax
|
||||
; AVX2-NEXT: vpinsrb $3, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_8: # %else8
|
||||
|
|
@ -865,10 +854,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: vpcmpeqb %xmm5, %xmm2, %xmm5
|
||||
; AVX2-NEXT: vpextrb $6, %xmm5, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: je .LBB3_14
|
||||
; AVX2-NEXT: # %bb.13: # %cond.load16
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm6
|
||||
; AVX2-NEXT: vmovq %xmm6, %rax
|
||||
; AVX2-NEXT: vmovq %xmm0, %rax
|
||||
; AVX2-NEXT: vpinsrb $6, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_14: # %else17
|
||||
; AVX2-NEXT: vpmovsxdq %xmm1, %ymm6
|
||||
|
|
@ -876,7 +865,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB3_16
|
||||
; AVX2-NEXT: # %bb.15: # %cond.load19
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX2-NEXT: vpinsrb $7, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_16: # %else20
|
||||
|
|
@ -902,10 +890,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: vpcmpeqb %xmm5, %xmm2, %xmm5
|
||||
; AVX2-NEXT: vpextrb $10, %xmm5, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: je .LBB3_22
|
||||
; AVX2-NEXT: # %bb.21: # %cond.load28
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm6
|
||||
; AVX2-NEXT: vmovq %xmm6, %rax
|
||||
; AVX2-NEXT: vmovq %xmm0, %rax
|
||||
; AVX2-NEXT: vpinsrb $10, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_22: # %else29
|
||||
; AVX2-NEXT: vpmovsxdq %xmm1, %ymm1
|
||||
|
|
@ -913,7 +901,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB3_24
|
||||
; AVX2-NEXT: # %bb.23: # %cond.load31
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX2-NEXT: vpinsrb $11, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_24: # %else32
|
||||
|
|
@ -938,17 +925,16 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm2, %xmm1
|
||||
; AVX2-NEXT: vpextrb $14, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: je .LBB3_30
|
||||
; AVX2-NEXT: # %bb.29: # %cond.load40
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2
|
||||
; AVX2-NEXT: vmovq %xmm2, %rax
|
||||
; AVX2-NEXT: vmovq %xmm0, %rax
|
||||
; AVX2-NEXT: vpinsrb $14, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_30: # %else41
|
||||
; AVX2-NEXT: vpextrb $15, %xmm1, %eax
|
||||
; AVX2-NEXT: testb $1, %al
|
||||
; AVX2-NEXT: je .LBB3_32
|
||||
; AVX2-NEXT: # %bb.31: # %cond.load43
|
||||
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm0
|
||||
; AVX2-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX2-NEXT: vpinsrb $15, (%rax), %xmm3, %xmm3
|
||||
; AVX2-NEXT: .LBB3_32: # %else44
|
||||
|
|
@ -1009,9 +995,9 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: kshiftrw $4, %k0, %k1
|
||||
; AVX512-NEXT: kmovw %k1, %eax
|
||||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: vextracti32x4 $2, %zmm4, %xmm5
|
||||
; AVX512-NEXT: je .LBB3_10
|
||||
; AVX512-NEXT: # %bb.9: # %cond.load10
|
||||
; AVX512-NEXT: vextracti32x4 $2, %zmm4, %xmm5
|
||||
; AVX512-NEXT: vmovq %xmm5, %rax
|
||||
; AVX512-NEXT: vpinsrb $4, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_10: # %else11
|
||||
|
|
@ -1020,7 +1006,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: je .LBB3_12
|
||||
; AVX512-NEXT: # %bb.11: # %cond.load13
|
||||
; AVX512-NEXT: vextracti32x4 $2, %zmm4, %xmm5
|
||||
; AVX512-NEXT: vpextrq $1, %xmm5, %rax
|
||||
; AVX512-NEXT: vpinsrb $5, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_12: # %else14
|
||||
|
|
@ -1032,10 +1017,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: kshiftrw $6, %k0, %k1
|
||||
; AVX512-NEXT: kmovw %k1, %eax
|
||||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: vextracti32x4 $3, %zmm4, %xmm4
|
||||
; AVX512-NEXT: je .LBB3_14
|
||||
; AVX512-NEXT: # %bb.13: # %cond.load16
|
||||
; AVX512-NEXT: vextracti32x4 $3, %zmm4, %xmm5
|
||||
; AVX512-NEXT: vmovq %xmm5, %rax
|
||||
; AVX512-NEXT: vmovq %xmm4, %rax
|
||||
; AVX512-NEXT: vpinsrb $6, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_14: # %else17
|
||||
; AVX512-NEXT: vpmovsxdq %ymm0, %zmm0
|
||||
|
|
@ -1044,7 +1029,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: je .LBB3_16
|
||||
; AVX512-NEXT: # %bb.15: # %cond.load19
|
||||
; AVX512-NEXT: vextracti32x4 $3, %zmm4, %xmm4
|
||||
; AVX512-NEXT: vpextrq $1, %xmm4, %rax
|
||||
; AVX512-NEXT: vpinsrb $7, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_16: # %else20
|
||||
|
|
@ -1098,9 +1082,9 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: kshiftrw $12, %k0, %k1
|
||||
; AVX512-NEXT: kmovw %k1, %eax
|
||||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm3
|
||||
; AVX512-NEXT: je .LBB3_26
|
||||
; AVX512-NEXT: # %bb.25: # %cond.load34
|
||||
; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm3
|
||||
; AVX512-NEXT: vmovq %xmm3, %rax
|
||||
; AVX512-NEXT: vpinsrb $12, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_26: # %else35
|
||||
|
|
@ -1109,7 +1093,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: je .LBB3_28
|
||||
; AVX512-NEXT: # %bb.27: # %cond.load37
|
||||
; AVX512-NEXT: vextracti32x4 $2, %zmm0, %xmm3
|
||||
; AVX512-NEXT: vpextrq $1, %xmm3, %rax
|
||||
; AVX512-NEXT: vpinsrb $13, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_28: # %else38
|
||||
|
|
@ -1120,10 +1103,10 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: kshiftrw $14, %k0, %k1
|
||||
; AVX512-NEXT: kmovw %k1, %eax
|
||||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm0
|
||||
; AVX512-NEXT: je .LBB3_30
|
||||
; AVX512-NEXT: # %bb.29: # %cond.load40
|
||||
; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm1
|
||||
; AVX512-NEXT: vmovq %xmm1, %rax
|
||||
; AVX512-NEXT: vmovq %xmm0, %rax
|
||||
; AVX512-NEXT: vpinsrb $14, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_30: # %else41
|
||||
; AVX512-NEXT: kshiftrw $15, %k0, %k0
|
||||
|
|
@ -1131,7 +1114,6 @@ define <16 x i8> @gather_v16i8_v16i32_v16i8(i8* %base, <16 x i32> %idx, <16 x i8
|
|||
; AVX512-NEXT: testb $1, %al
|
||||
; AVX512-NEXT: je .LBB3_32
|
||||
; AVX512-NEXT: # %bb.31: # %cond.load43
|
||||
; AVX512-NEXT: vextracti32x4 $3, %zmm0, %xmm0
|
||||
; AVX512-NEXT: vpextrq $1, %xmm0, %rax
|
||||
; AVX512-NEXT: vpinsrb $15, (%rax), %xmm2, %xmm2
|
||||
; AVX512-NEXT: .LBB3_32: # %else44
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue