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[AArch64] Allow -mattr=tpidr-el[1|2|3] 

Added subtarget features for AArch64 to use TPIDR_EL[1|2|3] as the TLS base
register, rather than the default TPIDR_EL0.

Patch by Philip Derrin!

Differential revision: https://reviews.llvm.org/D54685

llvm-svn: 356657
This commit is contained in:
Oliver Stannard 2019-03-21 11:30:17 +00:00
parent 54ed653870
commit defdb1070f
4 changed files with 30 additions and 0 deletions
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8
llvm/lib/Target/AArch64/AArch64.td
View File

@ -384,6 +384,14 @@ def AArch64InstrInfo : InstrInfo;
include "AArch64SystemOperands.td"
//===----------------------------------------------------------------------===//
// Access to privileged registers
//===----------------------------------------------------------------------===//
foreach i = 1-3 in
def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
"true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
//===----------------------------------------------------------------------===//
// AArch64 Processors supported.
//

6
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
View File

@ -505,6 +505,12 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
if (MF->getTarget().getTargetTriple().isOSFuchsia() &&
MF->getTarget().getCodeModel() == CodeModel::Kernel)
SysReg = AArch64SysReg::TPIDR_EL1;
else if (MF->getSubtarget<AArch64Subtarget>().useEL3ForTP())
SysReg = AArch64SysReg::TPIDR_EL3;
else if (MF->getSubtarget<AArch64Subtarget>().useEL2ForTP())
SysReg = AArch64SysReg::TPIDR_EL2;
else if (MF->getSubtarget<AArch64Subtarget>().useEL1ForTP())
SysReg = AArch64SysReg::TPIDR_EL1;
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
.addImm(SysReg);
MI.eraseFromParent();

7
llvm/lib/Target/AArch64/AArch64Subtarget.h
View File

@ -173,6 +173,9 @@ protected:
bool DisableLatencySchedHeuristic = false;
bool UseRSqrt = false;
bool Force32BitJumpTables = false;
bool UseEL1ForTP = false;
bool UseEL2ForTP = false;
bool UseEL3ForTP = false;
uint8_t MaxInterleaveFactor = 2;
uint8_t VectorInsertExtractBaseCost = 3;
uint16_t CacheLineSize = 0;
@ -324,6 +327,10 @@ public:
hasFuseCCSelect() || hasFuseLiterals();
}
bool useEL1ForTP() const { return UseEL1ForTP; }
bool useEL2ForTP() const { return UseEL2ForTP; }
bool useEL3ForTP() const { return UseEL3ForTP; }
bool useRSqrt() const { return UseRSqrt; }
bool force32BitJumpTables() const { return Force32BitJumpTables; }
unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }

9
llvm/test/CodeGen/AArch64/arm64-builtins-linux.ll
View File

@ -1,6 +1,9 @@
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; RUN: llc < %s -mtriple=aarch64-fuchsia | FileCheck %s
; RUN: llc < %s -mtriple=aarch64-fuchsia -code-model=kernel | FileCheck --check-prefix=FUCHSIA-KERNEL %s
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el1 | FileCheck --check-prefix=USEEL1 %s
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el2 | FileCheck --check-prefix=USEEL2 %s
; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+tpidr-el3 | FileCheck --check-prefix=USEEL3 %s
; Function Attrs: nounwind readnone
declare i8* @llvm.thread.pointer() #1
@ -10,6 +13,12 @@ define i8* @thread_pointer() {
; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0
; FUCHSIA-KERNEL: thread_pointer:
; FUCHSIA-KERNEL: mrs {{x[0-9]+}}, TPIDR_EL1
; USEEL1: thread_pointer:
; USEEL1: mrs {{x[0-9]+}}, TPIDR_EL1
; USEEL2: thread_pointer:
; USEEL2: mrs {{x[0-9]+}}, TPIDR_EL2
; USEEL3: thread_pointer:
; USEEL3: mrs {{x[0-9]+}}, TPIDR_EL3
%1 = tail call i8* @llvm.thread.pointer()
ret i8* %1
}