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[FastISel][AArch64] Allow handling of vectors during return lowering for little endian machines. 

Allow handling of vectors during return lowering at least for little endian machines.
This was restricted in r208200 to fix it for big endian machines (according to
the comment), but it also disabled it for little endian too.

llvm-svn: 217846
This commit is contained in:
Juergen Ributzka 2014-09-15 23:40:10 +00:00
parent b9e49c73ee
commit de47c47cc1
1 changed files with 7 additions and 2 deletions
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9
llvm/lib/Target/AArch64/AArch64FastISel.cpp
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@ -2871,11 +2871,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
const Value *RV = Ret->getOperand(0);
// Don't bother handling odd stuff for now.
if (VA.getLocInfo() != CCValAssign::Full)
if ((VA.getLocInfo() != CCValAssign::Full) &&
(VA.getLocInfo() != CCValAssign::BCvt))
return false;
// Only handle register returns for now.
if (!VA.isRegLoc())
return false;
unsigned Reg = getRegForValue(RV);
if (Reg == 0)
return false;
@ -2891,12 +2894,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) {
return false;
// Vectors (of > 1 lane) in big endian need tricky handling.
if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1)
if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 &&
!Subtarget->isLittleEndian())
return false;
MVT RVVT = RVEVT.getSimpleVT();
if (RVVT == MVT::f128)
return false;
MVT DestVT = VA.getValVT();
// Special handling for extended integers.
if (RVVT != DestVT) {