[PowerPC] Improve BUILD_VECTOR of 4 i32s
Currently, for this node:
vector int test(int a, int b, int c, int d) {
return (vector int) { a, b, c, d };
}
we get this on Power9:
mtvsrdd 34, 5, 3
mtvsrdd 35, 6, 4
vmrgow 2, 3, 2
and this on Power8:
mtvsrwz 0, 3
mtvsrwz 1, 5
mtvsrwz 2, 4
mtvsrwz 3, 6
xxmrghd 34, 1, 0
xxmrghd 35, 3, 2
vmrgow 2, 3, 2
This can be improved to this on LE Power9:
rldimi 3, 4, 32, 0
rldimi 5, 6, 32, 0
mtvsrdd 34, 5, 3
and this on LE Power8
rldimi 3, 4, 32, 0
rldimi 5, 6, 32, 0
mtvsrd 34, 3
mtvsrd 35, 5
xxpermdi 34, 35, 34, 0
This patch updates the TD pattern to generate the optimized sequence for both
Power8 and Power9 on LE and BE.
Differential Revision: https://reviews.llvm.org/D53494
llvm-svn: 345414
This commit is contained in:
Lei Huang
parent
3cc0e935c4
commit
de20843f6f
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@ -3873,10 +3873,11 @@ let AddedComplexity = 400 in {
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(COPY_TO_REGCLASS (MTVSRD $A), VSRC),
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(COPY_TO_REGCLASS (MTVSRD $B), VSRC), 0))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
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(VMRGOW (XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC),
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(COPY_TO_REGCLASS (MTVSRWZ $C), VSRC), 0),
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(XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $B), VSRC),
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(COPY_TO_REGCLASS (MTVSRWZ $D), VSRC), 0))>;
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(XXPERMDI
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(COPY_TO_REGCLASS
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(MTVSRD (RLDIMI AnyExts.B, AnyExts.A, 32, 0)), VSRC),
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(COPY_TO_REGCLASS
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(MTVSRD (RLDIMI AnyExts.D, AnyExts.C, 32, 0)), VSRC), 0)>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
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(XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
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}
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@ -3888,10 +3889,11 @@ let AddedComplexity = 400 in {
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(COPY_TO_REGCLASS (MTVSRD $B), VSRC),
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(COPY_TO_REGCLASS (MTVSRD $A), VSRC), 0))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
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(VMRGOW (XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $D), VSRC),
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(COPY_TO_REGCLASS (MTVSRWZ $B), VSRC), 0),
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(XXPERMDI (COPY_TO_REGCLASS (MTVSRWZ $C), VSRC),
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(COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 0))>;
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(XXPERMDI
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(COPY_TO_REGCLASS
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(MTVSRD (RLDIMI AnyExts.C, AnyExts.D, 32, 0)), VSRC),
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(COPY_TO_REGCLASS
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(MTVSRD (RLDIMI AnyExts.A, AnyExts.B, 32, 0)), VSRC), 0)>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$A, i32:$A, i32:$A)),
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(XXSPLTW (COPY_TO_REGCLASS (MTVSRWZ $A), VSRC), 1)>;
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}
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@ -3944,10 +3946,9 @@ let AddedComplexity = 400 in {
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def : Pat<(v2i64 (build_vector i64:$rB, i64:$rA)),
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(v2i64 (MTVSRDD $rB, $rA))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
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(VMRGOW
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(v4i32 (COPY_TO_REGCLASS (MTVSRDD AnyExts.A, AnyExts.C), VSRC)),
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(v4i32
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(COPY_TO_REGCLASS (MTVSRDD AnyExts.B, AnyExts.D), VSRC)))>;
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(MTVSRDD
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(RLDIMI AnyExts.B, AnyExts.A, 32, 0),
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(RLDIMI AnyExts.D, AnyExts.C, 32, 0))>;
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}
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let Predicates = [IsISA3_0, HasDirectMove, IsLittleEndian] in {
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@ -3957,10 +3958,9 @@ let AddedComplexity = 400 in {
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def : Pat<(v2i64 (build_vector i64:$rA, i64:$rB)),
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(v2i64 (MTVSRDD $rB, $rA))>;
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def : Pat<(v4i32 (build_vector i32:$A, i32:$B, i32:$C, i32:$D)),
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(VMRGOW
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(v4i32 (COPY_TO_REGCLASS (MTVSRDD AnyExts.D, AnyExts.B), VSRC)),
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(v4i32
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(COPY_TO_REGCLASS (MTVSRDD AnyExts.C, AnyExts.A), VSRC)))>;
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(MTVSRDD
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(RLDIMI AnyExts.C, AnyExts.D, 32, 0),
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(RLDIMI AnyExts.A, AnyExts.B, 32, 0))>;
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}
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// P9 Altivec instructions that can be used to build vectors.
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// Adding them to PPCInstrVSX.td rather than PPCAltivecVSX.td to compete
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@ -838,28 +838,26 @@ entry:
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; P9LE-LABEL: fromRegsi
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; P8BE-LABEL: fromRegsi
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; P8LE-LABEL: fromRegsi
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; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5
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; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6
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; P9BE: vmrgow v2, [[REG1]], [[REG2]]
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; P9BE-DAG: rldimi r6, r5, 32, 0
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; P9BE-DAG: rldimi r4, r3, 32, 0
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; P9BE: mtvsrdd v2, r4, r6
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; P9BE: blr
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; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3
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; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4
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; P9LE: vmrgow v2, [[REG2]], [[REG1]]
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; P9LE-DAG: rldimi r3, r4, 32, 0
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; P9LE-DAG: rldimi r5, r6, 32, 0
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; P9LE: mtvsrdd v2, r5, r3
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; P9LE: blr
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
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; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]]
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; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]]
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; P8BE: vmrgow v2, [[REG5]], [[REG6]]
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
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; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]]
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; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]]
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; P8LE: vmrgow v2, [[REG6]], [[REG5]]
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; P8BE-DAG: rldimi r6, r5, 32, 0
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; P8BE-DAG: rldimi r4, r3, 32, 0
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; P8BE-DAG: mtvsrd f[[REG1:[0-9]+]], r6
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; P8BE-DAG: mtvsrd f[[REG2:[0-9]+]], r4
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; P8BE-DAG: xxmrghd v2, vs[[REG2]], vs[[REG1]]
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; P8BE: blr
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; P8LE-DAG: rldimi r3, r4, 32, 0
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; P8LE-DAG: rldimi r5, r6, 32, 0
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; P8LE-DAG: mtvsrd f[[REG1:[0-9]+]], r3
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; P8LE-DAG: mtvsrd f[[REG2:[0-9]+]], r5
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; P8LE-DAG: xxmrghd v2, vs[[REG2]], vs[[REG1]]
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; P8LE: blr
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}
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; Function Attrs: norecurse nounwind readnone
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@ -1065,38 +1063,34 @@ entry:
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: rldimi
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; P9BE: rldimi
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; P9BE: mtvsrdd
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; P9BE: mtvsrdd
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; P9BE: vmrgow
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: rldimi
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; P9LE: rldimi
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; P9LE: mtvsrdd
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; P9LE: mtvsrdd
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; P9LE: vmrgow
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: rldimi
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; P8BE: rldimi
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; P8BE: mtvsrd
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; P8BE: mtvsrd
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; P8BE: xxmrghd
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; P8BE: xxmrghd
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; P8BE: vmrgow
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: rldimi
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; P8LE: rldimi
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; P8LE: mtvsrd
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; P8LE: mtvsrd
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; P8LE: xxmrghd
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; P8LE: xxmrghd
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; P8LE: vmrgow
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}
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; Function Attrs: norecurse nounwind readonly
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@ -1132,41 +1126,37 @@ entry:
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: rldimi
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; P9BE: rldimi
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; P9BE: mtvsrdd
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; P9BE: mtvsrdd
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; P9BE: vmrgow
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; P9LE: sldi r4, r4, 2
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: rldimi
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; P9LE: rldimi
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; P9LE: mtvsrdd
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; P9LE: mtvsrdd
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; P9LE: vmrgow
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; P8BE: sldi r4, r4, 2
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: rldimi
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; P8BE: rldimi
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; P8BE: mtvsrd
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; P8BE: mtvsrd
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; P8BE: xxmrghd
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; P8BE: xxmrghd
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; P8BE: vmrgow
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; P8LE: sldi r4, r4, 2
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: rldimi
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; P8LE: rldimi
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; P8LE: mtvsrd
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; P8LE: mtvsrd
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; P8LE: xxmrghd
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; P8LE: xxmrghd
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; P8LE: vmrgow
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}
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; Function Attrs: norecurse nounwind readnone
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@ -1978,28 +1968,26 @@ entry:
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; P9LE-LABEL: fromRegsui
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; P8BE-LABEL: fromRegsui
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; P8LE-LABEL: fromRegsui
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; P9BE-DAG: mtvsrdd [[REG1:v[0-9]+]], r3, r5
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; P9BE-DAG: mtvsrdd [[REG2:v[0-9]+]], r4, r6
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; P9BE: vmrgow v2, [[REG1]], [[REG2]]
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; P9BE-DAG: rldimi r6, r5, 32, 0
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; P9BE-DAG: rldimi r4, r3, 32, 0
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; P9BE: mtvsrdd v2, r4, r6
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; P9BE: blr
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; P9LE-DAG: mtvsrdd [[REG1:v[0-9]+]], r5, r3
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; P9LE-DAG: mtvsrdd [[REG2:v[0-9]+]], r6, r4
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; P9LE: vmrgow v2, [[REG2]], [[REG1]]
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; P9LE-DAG: rldimi r3, r4, 32, 0
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; P9LE-DAG: rldimi r5, r6, 32, 0
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; P9LE: mtvsrdd v2, r5, r3
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; P9LE: blr
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
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; P8BE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
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; P8BE-DAG: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG1]], {{[v][s]*}}[[REG3]]
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; P8BE-DAG: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG2]], {{[v][s]*}}[[REG4]]
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; P8BE: vmrgow v2, [[REG5]], [[REG6]]
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG1:[0-9]+]], r3
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG2:[0-9]+]], r4
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG3:[0-9]+]], r5
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; P8LE-DAG: mtvsrwz {{[vf]}}[[REG4:[0-9]+]], r6
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; P8LE: xxmrghd [[REG5:v[0-9]+]], {{[v][s]*}}[[REG3]], {{[v][s]*}}[[REG1]]
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; P8LE: xxmrghd [[REG6:v[0-9]+]], {{[v][s]*}}[[REG4]], {{[v][s]*}}[[REG2]]
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; P8LE: vmrgow v2, [[REG6]], [[REG5]]
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; P8BE-DAG: rldimi r6, r5, 32, 0
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; P8BE-DAG: rldimi r4, r3, 32, 0
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; P8BE-DAG: mtvsrd f[[REG1:[0-9]+]], r6
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; P8BE-DAG: mtvsrd f[[REG2:[0-9]+]], r4
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; P8BE-DAG: xxmrghd v2, vs[[REG2]], vs[[REG1]]
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; P8BE: blr
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; P8LE-DAG: rldimi r3, r4, 32, 0
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; P8LE-DAG: rldimi r5, r6, 32, 0
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; P8LE-DAG: mtvsrd f[[REG1:[0-9]+]], r3
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; P8LE-DAG: mtvsrd f[[REG2:[0-9]+]], r5
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; P8LE-DAG: xxmrghd v2, vs[[REG2]], vs[[REG1]]
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; P8LE: blr
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}
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; Function Attrs: norecurse nounwind readnone
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@ -2207,38 +2195,34 @@ entry:
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: rldimi
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; P9BE: rldimi
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; P9BE: mtvsrdd
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; P9BE: mtvsrdd
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; P9BE: vmrgow
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: rldimi
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; P9LE: rldimi
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; P9LE: mtvsrdd
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; P9LE: mtvsrdd
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; P9LE: vmrgow
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
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; P8BE: rldimi
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; P8BE: rldimi
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; P8BE: mtvsrd
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; P8BE: mtvsrd
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; P8BE: xxmrghd
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; P8BE: xxmrghd
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; P8BE: vmrgow
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: lwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: mtvsrwz
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; P8LE: rldimi
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; P8LE: rldimi
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; P8LE: mtvsrd
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; P8LE: mtvsrd
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; P8LE: xxmrghd
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; P8LE: xxmrghd
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; P8LE: vmrgow
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}
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; Function Attrs: norecurse nounwind readonly
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@ -2274,41 +2258,37 @@ entry:
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: lwz
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; P9BE: rldimi
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; P9BE: rldimi
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; P9BE: mtvsrdd
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; P9BE: mtvsrdd
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; P9BE: vmrgow
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; P9LE: sldi r4, r4, 2
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: lwz
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; P9LE: rldimi
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; P9LE: rldimi
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; P9LE: mtvsrdd
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; P9LE: mtvsrdd
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; P9LE: vmrgow
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; P8BE: sldi r4, r4, 2
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: lwz
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; P8BE: mtvsrwz
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; P8BE: mtvsrwz
|
||||
; P8BE: mtvsrwz
|
||||
; P8BE: mtvsrwz
|
||||
; P8BE: rldimi
|
||||
; P8BE: rldimi
|
||||
; P8BE: mtvsrd
|
||||
; P8BE: mtvsrd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: xxmrghd
|
||||
; P8BE: vmrgow
|
||||
; P8LE: sldi r4, r4, 2
|
||||
; P8LE: lwz
|
||||
; P8LE: lwz
|
||||
; P8LE: lwz
|
||||
; P8LE: lwz
|
||||
; P8LE: mtvsrwz
|
||||
; P8LE: mtvsrwz
|
||||
; P8LE: mtvsrwz
|
||||
; P8LE: mtvsrwz
|
||||
; P8LE: rldimi
|
||||
; P8LE: rldimi
|
||||
; P8LE: mtvsrd
|
||||
; P8LE: mtvsrd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: xxmrghd
|
||||
; P8LE: vmrgow
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
|
|
|
|||
Loading…
Reference in New Issue