Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. llvm-svn: 132314
This commit is contained in:
parent
ea8ca34e3a
commit
ddffa0e160
|
@ -151,6 +151,14 @@ class DwarfRegNum<list<int> Numbers> {
|
||||||
list<int> DwarfNumbers = Numbers;
|
list<int> DwarfNumbers = Numbers;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// DwarfRegAlias - This class declares that a given register uses the same dwarf
|
||||||
|
// numbers as another one. This is useful for making it clear that the two
|
||||||
|
// registers do have the same number. It also lets us build a mapping
|
||||||
|
// from dwarf register number to llvm register.
|
||||||
|
class DwarfRegAlias<Register reg> {
|
||||||
|
Register DwarfAlias = reg;
|
||||||
|
}
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// Pull in the common support for scheduling
|
// Pull in the common support for scheduling
|
||||||
//
|
//
|
||||||
|
|
|
@ -188,22 +188,22 @@ let Namespace = "X86" in {
|
||||||
|
|
||||||
// YMM Registers, used by AVX instructions
|
// YMM Registers, used by AVX instructions
|
||||||
let SubRegIndices = [sub_xmm] in {
|
let SubRegIndices = [sub_xmm] in {
|
||||||
def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>;
|
def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias<XMM0>;
|
||||||
def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>;
|
def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias<XMM1>;
|
||||||
def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>;
|
def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias<XMM2>;
|
||||||
def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>;
|
def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias<XMM3>;
|
||||||
def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>;
|
def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias<XMM4>;
|
||||||
def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>;
|
def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias<XMM5>;
|
||||||
def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>;
|
def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias<XMM6>;
|
||||||
def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>;
|
def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias<XMM7>;
|
||||||
def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>;
|
def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias<XMM8>;
|
||||||
def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>;
|
def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias<XMM9>;
|
||||||
def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>;
|
def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias<XMM10>;
|
||||||
def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>;
|
def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias<XMM11>;
|
||||||
def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>;
|
def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias<XMM12>;
|
||||||
def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>;
|
def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias<XMM13>;
|
||||||
def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>;
|
def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias<XMM14>;
|
||||||
def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>;
|
def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias<XMM15>;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Floating point stack registers
|
// Floating point stack registers
|
||||||
|
|
|
@ -989,6 +989,17 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
|
||||||
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
|
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
|
||||||
I->second.push_back(-1);
|
I->second.push_back(-1);
|
||||||
|
|
||||||
|
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
|
||||||
|
Record *Reg = Regs[i].TheDef;
|
||||||
|
const RecordVal *V = Reg->getValue("DwarfAlias");
|
||||||
|
if (!V || !V->getValue())
|
||||||
|
continue;
|
||||||
|
|
||||||
|
DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
|
||||||
|
Record *Alias = DI->getDef();
|
||||||
|
DwarfRegNums[Reg] = DwarfRegNums[Alias];
|
||||||
|
}
|
||||||
|
|
||||||
// Emit information about the dwarf register numbers.
|
// Emit information about the dwarf register numbers.
|
||||||
OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
|
OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
|
||||||
<< "unsigned Flavour) const {\n"
|
<< "unsigned Flavour) const {\n"
|
||||||
|
|
Loading…
Reference in New Issue