AMDGPU/GlobalISel: Mark 32-bit float constants as legal
Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 llvm-svn: 304003
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@ -36,6 +36,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
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setAction({G_CONSTANT, S32}, Legal);
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setAction({G_CONSTANT, S64}, Legal);
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setAction({G_FCONSTANT, S32}, Legal);
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setAction({G_GEP, P1}, Legal);
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setAction({G_GEP, P2}, Legal);
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setAction({G_GEP, 1, S64}, Legal);
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@ -2331,6 +2331,10 @@ static bool isSubRegOf(const SIRegisterInfo &TRI,
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bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const {
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uint16_t Opcode = MI.getOpcode();
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if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
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return true;
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const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
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@ -5,6 +5,11 @@
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entry:
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ret void
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}
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define void @test_fconstant() {
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entry:
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ret void
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}
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...
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---
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@ -18,3 +23,18 @@ body: |
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%0(s32) = G_CONSTANT i32 5
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...
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---
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name: test_fconstant
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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body: |
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bb.0.entry:
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; CHECK-LABEL: name: test_fconstant
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; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
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; CHECK: %1(s32) = G_FCONSTANT float 7.5
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%0(s32) = G_FCONSTANT float 1.0
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%1(s32) = G_FCONSTANT float 7.5
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...
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