Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
llvm-svn: 117294
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@ -2951,28 +2951,30 @@ def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
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// VBIF : Vector Bitwise Insert if False
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// like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
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// FIXME: This instruction's encoding MAY NOT BE correct.
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def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
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(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
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(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
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N3RegFrm, IIC_VBINiD,
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"vbif", "$dst, $src2, $src3", "$src1 = $dst",
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"vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
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[/* For disassembly only; pattern left blank */]>;
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def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
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(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
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(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
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N3RegFrm, IIC_VBINiQ,
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"vbif", "$dst, $src2, $src3", "$src1 = $dst",
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"vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
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[/* For disassembly only; pattern left blank */]>;
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// VBIT : Vector Bitwise Insert if True
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// like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
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// FIXME: This instruction's encoding MAY NOT BE correct.
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def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
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(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3),
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(outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
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N3RegFrm, IIC_VBINiD,
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"vbit", "$dst, $src2, $src3", "$src1 = $dst",
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"vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
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[/* For disassembly only; pattern left blank */]>;
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def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
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(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3),
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(outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
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N3RegFrm, IIC_VBINiQ,
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"vbit", "$dst, $src2, $src3", "$src1 = $dst",
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"vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
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[/* For disassembly only; pattern left blank */]>;
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// VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
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@ -3,6 +3,7 @@
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; FIXME: The following instructions still require testing:
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; - vand with immediate
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; - vmvn of an immediate
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; - both vbit and vbif
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; CHECK: vand_8xi8
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define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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