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Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 

llvm-svn: 117294
This commit is contained in:
Owen Anderson 2010-10-25 20:17:22 +00:00
parent dea09c7564
commit dd001b89d7
2 changed files with 12 additions and 9 deletions
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18
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -2951,28 +2951,30 @@ def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
// VBIF : Vector Bitwise Insert if False // VBIF : Vector Bitwise Insert if False
// like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst", // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
// FIXME: This instruction's encoding MAY NOT BE correct.
def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1, def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
N3RegFrm, IIC_VBINiD, N3RegFrm, IIC_VBINiD,
"vbif", "$dst, $src2, $src3", "$src1 = $dst", "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>;
def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1, def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
N3RegFrm, IIC_VBINiQ, N3RegFrm, IIC_VBINiQ,
"vbif", "$dst, $src2, $src3", "$src1 = $dst", "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>;
// VBIT : Vector Bitwise Insert if True // VBIT : Vector Bitwise Insert if True
// like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst", // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
// FIXME: This instruction's encoding MAY NOT BE correct.
def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1, def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
(outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
N3RegFrm, IIC_VBINiD, N3RegFrm, IIC_VBINiD,
"vbit", "$dst, $src2, $src3", "$src1 = $dst", "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>;
def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1, def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
(outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
N3RegFrm, IIC_VBINiQ, N3RegFrm, IIC_VBINiQ,
"vbit", "$dst, $src2, $src3", "$src1 = $dst", "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>;
// VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking

1
llvm/test/MC/ARM/neon-bitwise-encoding.ll
View File

@ -3,6 +3,7 @@
; FIXME: The following instructions still require testing: ; FIXME: The following instructions still require testing:
; - vand with immediate ; - vand with immediate
; - vmvn of an immediate ; - vmvn of an immediate
; - both vbit and vbif
; CHECK: vand_8xi8 ; CHECK: vand_8xi8
define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i8> @vand_8xi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {