[AArch64][v8.5A] Add Armv8.5-A random number instructions
This adds two new system registers, used to generate random numbers. This is an optional extension to v8.5-A, and will be controlled by the "+rng" modifier of the -march= and -mcpu= options. Patch by Pablo Barrio! Differential revision: https://reviews.llvm.org/D52481 llvm-svn: 343217
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@ -70,6 +70,7 @@ AARCH64_ARCH_EXT_NAME("profile", AArch64::AEK_PROFILE, "+spe", "-spe")
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AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
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AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
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AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
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AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
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AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
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AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
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AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
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#undef AARCH64_ARCH_EXT_NAME
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#undef AARCH64_ARCH_EXT_NAME
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#ifndef AARCH64_CPU_NAME
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#ifndef AARCH64_CPU_NAME
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@ -180,6 +180,7 @@ enum ArchExtKind : unsigned {
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AEK_SHA2 = 1 << 15,
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AEK_SHA2 = 1 << 15,
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AEK_AES = 1 << 16,
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AEK_AES = 1 << 16,
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AEK_FP16FML = 1 << 17,
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AEK_FP16FML = 1 << 17,
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AEK_RAND = 1 << 18,
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};
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};
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StringRef getCanonicalArchName(StringRef Arch);
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StringRef getCanonicalArchName(StringRef Arch);
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@ -220,6 +220,9 @@ def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
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def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
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def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
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"true", "Enable Cache Clean to Point of Deep Persistence" >;
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"true", "Enable Cache Clean to Point of Deep Persistence" >;
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def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
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"true", "Enable Random Number generation instructions" >;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Architectures.
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// Architectures.
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//
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//
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@ -100,6 +100,7 @@ protected:
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bool HasSpecCtrl = false;
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bool HasSpecCtrl = false;
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bool HasPredCtrl = false;
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bool HasPredCtrl = false;
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bool HasCCDP = false;
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bool HasCCDP = false;
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bool HasRandGen = false;
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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bool HasZeroCycleRegMove = false;
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bool HasZeroCycleRegMove = false;
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@ -318,6 +319,7 @@ public:
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bool hasSpecCtrl() { return HasSpecCtrl; }
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bool hasSpecCtrl() { return HasSpecCtrl; }
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bool hasPredCtrl() { return HasPredCtrl; }
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bool hasPredCtrl() { return HasPredCtrl; }
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bool hasCCDP() { return HasCCDP; }
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bool hasCCDP() { return HasCCDP; }
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bool hasRandGen() { return HasRandGen; }
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bool isLittleEndian() const { return IsLittle; }
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bool isLittleEndian() const { return IsLittle; }
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@ -614,6 +614,13 @@ def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;
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def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
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def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
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}
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}
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// v8.5a "random number" registers
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::FeatureRandGen} }] in {
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def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>;
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def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>;
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}
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//===----------------------
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//===----------------------
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// Write-only regs
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// Write-only regs
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//===----------------------
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//===----------------------
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@ -0,0 +1,17 @@
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// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+rand < %s 2>&1| FileCheck %s
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mrs rndr
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mrs rndrrs
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rndr
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rndrrs
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mrs rndr, x0
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mrs rndrrs, x1
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rndr
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// CHECK: invalid operand for instruction
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// CHECK-NEXT: rndrrs
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@ -0,0 +1,14 @@
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// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+rand < %s | FileCheck %s
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// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NORAND
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// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-rand < %s 2>&1 | FileCheck %s --check-prefix=NORAND
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mrs x0, rndr
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mrs x1, rndrrs
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// CHECK: mrs x0, RNDR // encoding: [0x00,0x24,0x3b,0xd5]
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// CHECK: mrs x1, RNDRRS // encoding: [0x21,0x24,0x3b,0xd5]
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// NORAND: expected readable system register
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// NORAND-NEXT: rndr
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// NORAND: expected readable system register
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// NORAND-NEXT: rndrrs
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@ -0,0 +1,12 @@
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# RUN: llvm-mc -triple=aarch64 -mattr=+rand -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NORAND
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# RUN: llvm-mc -triple=aarch64 -mattr=-rand -disassemble < %s | FileCheck %s --check-prefix=NORAND
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[0x00,0x24,0x3b,0xd5]
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[0x21,0x24,0x3b,0xd5]
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# CHECK: mrs x0, RNDR
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# CHECK: mrs x1, RNDRRS
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# NORAND: mrs x0, S3_3_C2_C4_0
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# NORAND: mrs x1, S3_3_C2_C4_1
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@ -967,7 +967,8 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
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{"rdm", "nordm", "+rdm", "-rdm"},
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{"rdm", "nordm", "+rdm", "-rdm"},
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{"sve", "nosve", "+sve", "-sve"},
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{"sve", "nosve", "+sve", "-sve"},
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{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
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{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
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{"rcpc", "norcpc", "+rcpc", "-rcpc" }};
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{"rcpc", "norcpc", "+rcpc", "-rcpc" },
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{"rng", "norng", "+rand", "-rand"}};
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for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
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for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
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EXPECT_EQ(StringRef(ArchExt[i][2]),
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EXPECT_EQ(StringRef(ArchExt[i][2]),
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