[AArch64] Corrected FP16 Intrinsic range checks in Clang + added Sema tests
Summary: This fixes the ranges for the vcvth family of FP16 intrinsics in the clang front end. Previously it was accepting incorrect ranges -Changed builtin range checking in SemaChecking -added tests SemaCheck changes - included in their own file since no similar one exists -modified existing tests to reflect new ranges Reviewers: SjoerdMeijer, javed.absar Reviewed By: SjoerdMeijer Subscribers: kristof.beyls, cfe-commits Differential Revision: https://reviews.llvm.org/D47592 llvm-svn: 334489
This commit is contained in:
Luke Geeson
parent
dc82aa44e6
commit
dc54b37414
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@ -75,15 +75,15 @@ let ArchGuard = "defined(__ARM_FEATURE_FP16_SCALAR_ARITHMETIC) && defined(__aarc
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def SCALAR_FCVTPUH : SInst<"vcvtp_u16", "bs", "Sh">;
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def SCALAR_FCVTPUH1 : SInst<"vcvtp_u32", "Us", "Sh">;
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def SCALAR_FCVTPUH2 : SInst<"vcvtp_u64", "Os", "Sh">;
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def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "silUsUiUl">;
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def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">;
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def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">;
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def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">;
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def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "bsi", "Sh">;
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def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "Usi", "Sh">;
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def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "Osi", "Sh">;
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let isVCVT_N = 1 in {
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def SCALAR_SCVTFSHO : SInst<"vcvth_n_f16", "Ysi", "silUsUiUl">;
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def SCALAR_FCVTZSHO : SInst<"vcvt_n_s16", "$si", "Sh">;
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def SCALAR_FCVTZSH1O: SInst<"vcvt_n_s32", "Isi", "Sh">;
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def SCALAR_FCVTZSH2O: SInst<"vcvt_n_s64", "Lsi", "Sh">;
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def SCALAR_FCVTZUHO : SInst<"vcvt_n_u16", "bsi", "Sh">;
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def SCALAR_FCVTZUH1O: SInst<"vcvt_n_u32", "Usi", "Sh">;
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def SCALAR_FCVTZUH2O: SInst<"vcvt_n_u64", "Osi", "Sh">;
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}
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// Comparison
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def SCALAR_CMEQRH : SInst<"vceq", "bss", "Sh">;
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def SCALAR_CMEQZH : SInst<"vceqz", "bs", "Sh">;
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@ -1499,10 +1499,10 @@ bool Sema::CheckNeonBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
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switch (BuiltinID) {
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default:
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return false;
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#define GET_NEON_IMMEDIATE_CHECK
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#include "clang/Basic/arm_neon.inc"
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#include "clang/Basic/arm_fp16.inc"
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#undef GET_NEON_IMMEDIATE_CHECK
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#define GET_NEON_IMMEDIATE_CHECK
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#include "clang/Basic/arm_neon.inc"
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#include "clang/Basic/arm_fp16.inc"
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#undef GET_NEON_IMMEDIATE_CHECK
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}
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return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
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@ -486,90 +486,90 @@ uint16_t test_vclth_f16(float16_t a, float16_t b) {
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// CHECK-LABEL: test_vcvth_n_f16_s16
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// CHECK: [[SEXT:%.*]] = sext i16 %a to i32
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 [[SEXT]], i32 0)
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 [[SEXT]], i32 1)
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// CHECK: ret half [[CVT]]
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float16_t test_vcvth_n_f16_s16(int16_t a) {
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return vcvth_n_f16_s16(a, 0);
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return vcvth_n_f16_s16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_f16_s32
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 0)
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i32(i32 %a, i32 1)
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// CHECK: ret half [[CVT]]
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float16_t test_vcvth_n_f16_s32(int32_t a) {
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return vcvth_n_f16_s32(a, 0);
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return vcvth_n_f16_s32(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_f16_s64
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 0)
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 1)
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// CHECK: ret half [[CVT]]
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float16_t test_vcvth_n_f16_s64(int64_t a) {
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return vcvth_n_f16_s64(a, 0);
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return vcvth_n_f16_s64(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_s16_f16
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 0)
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
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// CHECK: [[RET:%.*]] = trunc i32 [[CVT]] to i16
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// CHECK: ret i16 [[RET]]
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int16_t test_vcvth_n_s16_f16(float16_t a) {
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return vcvth_n_s16_f16(a, 0);
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return vcvth_n_s16_f16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_s32_f16
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 0)
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxs.i32.f16(half %a, i32 1)
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// CHECK: ret i32 [[CVT]]
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int32_t test_vcvth_n_s32_f16(float16_t a) {
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return vcvth_n_s32_f16(a, 0);
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return vcvth_n_s32_f16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_s64_f16
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// CHECK: [[CVT:%.*]] = call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 0)
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// CHECK: [[CVT:%.*]] = call i64 @llvm.aarch64.neon.vcvtfp2fxs.i64.f16(half %a, i32 1)
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// CHECK: ret i64 [[CVT]]
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int64_t test_vcvth_n_s64_f16(float16_t a) {
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return vcvth_n_s64_f16(a, 0);
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return vcvth_n_s64_f16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_f16_u16
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// CHECK: [[SEXT:%.*]] = zext i16 %a to i32
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 [[SEXT]], i32 0)
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 [[SEXT]], i32 1)
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// CHECK: ret half [[CVT]]
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float16_t test_vcvth_n_f16_u16(int16_t a) {
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return vcvth_n_f16_u16(a, 0);
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return vcvth_n_f16_u16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_f16_u32
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 0)
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 1)
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// CHECK: ret half [[CVT]]
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float16_t test_vcvth_n_f16_u32(int32_t a) {
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return vcvth_n_f16_u32(a, 0);
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return vcvth_n_f16_u32(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_f16_u64
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i64(i64 %a, i32 0)
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// CHECK: [[CVT:%.*]] = call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i64(i64 %a, i32 1)
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// CHECK: ret half [[CVT]]
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float16_t test_vcvth_n_f16_u64(int64_t a) {
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return vcvth_n_f16_u64(a, 0);
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return vcvth_n_f16_u64(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_u16_f16
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 0)
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
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// CHECK: [[RET:%.*]] = trunc i32 [[CVT]] to i16
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// CHECK: ret i16 [[RET]]
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int16_t test_vcvth_n_u16_f16(float16_t a) {
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return vcvth_n_u16_f16(a, 0);
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return vcvth_n_u16_f16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_u32_f16
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 0)
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// CHECK: [[CVT:%.*]] = call i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half %a, i32 1)
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// CHECK: ret i32 [[CVT]]
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int32_t test_vcvth_n_u32_f16(float16_t a) {
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return vcvth_n_u32_f16(a, 0);
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return vcvth_n_u32_f16(a, 1);
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}
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// CHECK-LABEL: test_vcvth_n_u64_f16
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// CHECK: [[CVT:%.*]] = call i64 @llvm.aarch64.neon.vcvtfp2fxu.i64.f16(half %a, i32 0)
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// CHECK: [[CVT:%.*]] = call i64 @llvm.aarch64.neon.vcvtfp2fxu.i64.f16(half %a, i32 1)
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// CHECK: ret i64 [[CVT]]
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int64_t test_vcvth_n_u64_f16(float16_t a) {
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return vcvth_n_u64_f16(a, 0);
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return vcvth_n_u64_f16(a, 1);
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}
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// CHECK-LABEL: test_vdivh_f16
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@ -0,0 +1,64 @@
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// RUN: %clang_cc1 -triple arm64-linux-gnu -fallow-half-arguments-and-returns -target-feature +neon -target-feature +fullfp16 -ffreestanding -fsyntax-only -verify %s
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// RUN: %clang_cc1 -triple aarch64-linux-gnu -fallow-half-arguments-and-returns -target-feature +fullfp16 -target-feature +neon -ffreestanding -fsyntax-only -verify %s
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#include <arm_neon.h>
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#include <arm_fp16.h>
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void test_vcvt_f16_16(int16_t a){
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vcvth_n_f16_s16(a, 1);
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vcvth_n_f16_s16(a, 16);
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vcvth_n_f16_s16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_s16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_u16(a, 1);
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vcvth_n_f16_u16(a, 16);
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vcvth_n_f16_u16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_u16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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}
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void test_vcvt_f16_32(int32_t a){
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vcvth_n_f16_u32(a, 1);
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vcvth_n_f16_u32(a, 16);
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vcvth_n_f16_u32(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_u32(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_s32(a, 1);
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vcvth_n_f16_s32(a, 16);
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vcvth_n_f16_s32(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_s32(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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}
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void test_vcvt_f16_64(int64_t a){
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vcvth_n_f16_s64(a, 1);
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vcvth_n_f16_s64(a, 16);
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vcvth_n_f16_s64(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_f16_s64(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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}
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void test_vcvt_su_f(float16_t a){
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vcvth_n_s16_f16(a, 1);
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vcvth_n_s16_f16(a, 16);
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vcvth_n_s16_f16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_s16_f16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_s32_f16(a, 1);
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vcvth_n_s32_f16(a, 16);
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vcvth_n_s32_f16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_s32_f16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_s64_f16(a, 1);
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vcvth_n_s64_f16(a, 16);
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vcvth_n_s64_f16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_s64_f16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_u16_f16(a, 1);
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vcvth_n_u16_f16(a, 16);
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vcvth_n_u16_f16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_u16_f16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_u32_f16(a, 1);
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vcvth_n_u32_f16(a, 16);
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vcvth_n_u32_f16(a, 0); // expected-error {{argument should be a value from 1 to 16}}
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vcvth_n_u32_f16(a, 17); // expected-error {{argument should be a value from 1 to 16}}
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}
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@ -2162,8 +2162,7 @@ void NeonEmitter::genOverloadTypeCheckCode(raw_ostream &OS,
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OS << "#endif\n\n";
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}
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void
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NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
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void NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
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SmallVectorImpl<Intrinsic *> &Defs) {
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OS << "#ifdef GET_NEON_IMMEDIATE_CHECK\n";
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@ -2188,11 +2187,15 @@ NeonEmitter::genIntrinsicRangeCheckCode(raw_ostream &OS,
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Record *R = Def->getRecord();
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if (R->getValueAsBit("isVCVT_N")) {
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// VCVT between floating- and fixed-point values takes an immediate
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// in the range [1, 32) for f32 or [1, 64) for f64.
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// in the range [1, 32) for f32 or [1, 64) for f64 or [1, 16) for f16.
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LowerBound = "1";
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if (Def->getBaseType().getElementSizeInBits() == 32)
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if (Def->getBaseType().getElementSizeInBits() == 16 ||
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Def->getName().find('h') != std::string::npos)
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// VCVTh operating on FP16 intrinsics in range [1, 16)
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UpperBound = "15";
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else if (Def->getBaseType().getElementSizeInBits() == 32)
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UpperBound = "31";
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else
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else
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UpperBound = "63";
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} else if (R->getValueAsBit("isScalarShift")) {
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// Right shifts have an 'r' in the name, left shifts do not. Convert
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