[SparcV9] Add support for JIT in Sparc64.
With this change, all supported tests in test/ExecutionEngine pass in sparcv9. llvm-svn: 199977
This commit is contained in:
Venkatraman Govindaraju
parent
e758ddcd16
commit
dc3bcc19cf
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@ -68,9 +68,13 @@ static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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// The default 32-bit code model is abs32/pic32.
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if (CM == CodeModel::Default)
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CM = RM == Reloc::PIC_ ? CodeModel::Medium : CodeModel::Small;
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// The default 32-bit code model is abs32/pic32 and the default 32-bit
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// code model for JIT is abs32.
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switch (CM) {
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default: break;
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case CodeModel::Default:
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case CodeModel::JITDefault: CM = CodeModel::Small; break;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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@ -81,9 +85,17 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM,
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CodeGenOpt::Level OL) {
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MCCodeGenInfo *X = new MCCodeGenInfo();
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// The default 64-bit code model is abs44/pic32.
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if (CM == CodeModel::Default)
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CM = CodeModel::Medium;
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// The default 64-bit code model is abs44/pic32 and the default 64-bit
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// code model for JIT is abs64.
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switch (CM) {
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default: break;
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case CodeModel::Default:
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CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
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break;
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case CodeModel::JITDefault:
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CM = CodeModel::Large;
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break;
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}
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X->InitMCCodeGenInfo(RM, CM, OL);
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return X;
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@ -207,11 +207,11 @@ unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
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case SPII::MO_NO_FLAG: break;
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case SPII::MO_LO: return SP::reloc_sparc_lo;
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case SPII::MO_HI: return SP::reloc_sparc_hi;
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case SPII::MO_H44:
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case SPII::MO_M44:
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case SPII::MO_L44:
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case SPII::MO_HH:
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case SPII::MO_HM: assert(0 && "FIXME: Implement Medium/Large code model.");
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case SPII::MO_H44: return SP::reloc_sparc_h44;
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case SPII::MO_M44: return SP::reloc_sparc_m44;
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case SPII::MO_L44: return SP::reloc_sparc_l44;
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case SPII::MO_HH: return SP::reloc_sparc_hh;
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case SPII::MO_HM: return SP::reloc_sparc_hm;
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}
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unsigned Opc = MI.getOpcode();
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@ -1812,7 +1812,6 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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switch(getTargetMachine().getCodeModel()) {
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default:
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llvm_unreachable("Unsupported absolute code model");
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case CodeModel::JITDefault:
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case CodeModel::Small:
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// abs32.
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return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
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@ -12,7 +12,9 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "jit"
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#include "SparcJITInfo.h"
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#include "Sparc.h"
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#include "SparcRelocations.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/Support/Memory.h"
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@ -34,18 +36,17 @@ extern "C" {
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"SparcCompilationCallback:\n"
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// Save current register window.
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"\tsave %sp, -192, %sp\n"
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// stubaddr+4 is in %g1.
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// stubaddr is in %g1.
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"\tcall SparcCompilationCallbackC\n"
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"\t sub %g1, 4, %o0\n"
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"\t mov %g1, %o0\n"
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// restore original register window and
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// copy %o0 to %g1
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"\t restore %o0, 0, %g1\n"
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"\trestore %o0, 0, %g1\n"
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// call the new stub
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"\tjmp %g1\n"
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"\t nop\n"
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"\t.size SparcCompilationCallback, .-SparcCompilationCallback"
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);
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#else
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void SparcCompilationCallback() {
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llvm_unreachable(
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@ -54,75 +55,171 @@ extern "C" {
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#endif
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}
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#define HI(Val) (((unsigned)(Val)) >> 10)
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#define LO(Val) (((unsigned)(Val)) & 0x3FF)
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#define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF))
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#define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \
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| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
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#define NOP_INST SETHI_INST(0, 0)
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#define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
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| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
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#define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \
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| ((rs1) << 14) | (0 << 13) | ((rs2) & 0x1F))
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#define RDPC_INST(rd) (0x80000000 | ((rd) << 25) | (0x28 << 19) \
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| (5 << 14))
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#define LDX_INST(rs1, imm, rd) (0xC0000000 | ((rd) << 25) | (0x0B << 19) \
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| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
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#define SLLX_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x25 << 19) \
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| ((rs1) << 14) | (3 << 12) | ((imm) & 0x3F))
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#define SUB_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x04 << 19) \
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| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
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#define XOR_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x03 << 19) \
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| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
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#define BA_INST(tgt) (0x10800000 | ((tgt) & 0x3FFFFF))
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// Emit instructions to jump to Addr and store the starting address of
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// the instructions emitted in the scratch register.
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static void emitInstrForIndirectJump(intptr_t Addr,
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unsigned scratch,
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SmallVectorImpl<uint32_t> &Insts) {
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if (isInt<13>(Addr)) {
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// Emit: jmpl %g0+Addr, <scratch>
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// nop
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Insts.push_back(JMP_INST(0, LO10(Addr), scratch));
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Insts.push_back(NOP_INST);
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return;
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}
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if (isUInt<32>(Addr)) {
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// Emit: sethi %hi(Addr), scratch
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// jmpl scratch+%lo(Addr), scratch
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// sub scratch, 4, scratch
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Insts.push_back(SETHI_INST(HI22(Addr), scratch));
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Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
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Insts.push_back(SUB_INST(scratch, 4, scratch));
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return;
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}
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if (Addr < 0 && isInt<33>(Addr)) {
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// Emit: sethi %hix(Addr), scratch)
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// xor scratch, %lox(Addr), scratch
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// jmpl scratch+0, scratch
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// sub scratch, 8, scratch
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Insts.push_back(SETHI_INST(HIX22(Addr), scratch));
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Insts.push_back(XOR_INST(scratch, LOX10(Addr), scratch));
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Insts.push_back(JMP_INST(scratch, 0, scratch));
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Insts.push_back(SUB_INST(scratch, 8, scratch));
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return;
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}
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// Emit: rd %pc, scratch
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// ldx [scratch+16], scratch
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// jmpl scratch+0, scratch
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// sub scratch, 8, scratch
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// <Addr: 8 byte>
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Insts.push_back(RDPC_INST(scratch));
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Insts.push_back(LDX_INST(scratch, 16, scratch));
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Insts.push_back(JMP_INST(scratch, 0, scratch));
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Insts.push_back(SUB_INST(scratch, 8, scratch));
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Insts.push_back((uint32_t)(((int64_t)Addr) >> 32) & 0xffffffff);
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Insts.push_back((uint32_t)(Addr & 0xffffffff));
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// Instruction sequence without rdpc instruction
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// 7 instruction and 2 scratch register
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// Emit: sethi %hh(Addr), scratch
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// or scratch, %hm(Addr), scratch
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// sllx scratch, 32, scratch
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// sethi %hi(Addr), scratch2
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// or scratch, scratch2, scratch
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// jmpl scratch+%lo(Addr), scratch
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// sub scratch, 20, scratch
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// Insts.push_back(SETHI_INST(HH22(Addr), scratch));
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// Insts.push_back(OR_INST_I(scratch, HM10(Addr), scratch));
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// Insts.push_back(SLLX_INST(scratch, 32, scratch));
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// Insts.push_back(SETHI_INST(HI22(Addr), scratch2));
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// Insts.push_back(OR_INST_R(scratch, scratch2, scratch));
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// Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch));
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// Insts.push_back(SUB_INST(scratch, 20, scratch));
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}
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extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) {
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// Get the address of the compiled code for this function.
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intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
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// Rewrite the function stub so that we don't end up here every time we
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// execute the call. We're replacing the first three instructions of the
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// stub with code that jumps to the compiled function:
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// sethi %hi(NewVal), %g1
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// jmp %g1+%lo(NewVal)
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// nop
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// execute the call. We're replacing the stub instructions with code
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// that jumps to the compiled function:
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*(intptr_t *)(StubAddr) = SETHI_INST(HI(NewVal), 1);
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*(intptr_t *)(StubAddr + 4) = JMP_INST(1, LO(NewVal), 0);
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*(intptr_t *)(StubAddr + 8) = NOP_INST;
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SmallVector<uint32_t, 8> Insts;
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intptr_t diff = (NewVal - StubAddr) >> 2;
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if (isInt<22>(diff)) {
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// Use branch instruction to jump
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Insts.push_back(BA_INST(diff));
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Insts.push_back(NOP_INST);
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} else {
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// Otherwise, use indirect jump to the compiled function
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emitInstrForIndirectJump(NewVal, 1, Insts);
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}
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sys::Memory::InvalidateInstructionCache((void*) StubAddr, 12);
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for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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*(uint32_t *)(StubAddr + i*4) = Insts[i];
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sys::Memory::InvalidateInstructionCache((void*) StubAddr, Insts.size() * 4);
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return (void*)StubAddr;
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}
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void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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assert(0 && "FIXME: Implement SparcJITInfo::replaceMachineCodeForFunction");
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}
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TargetJITInfo::StubLayout SparcJITInfo::getStubLayout() {
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// The stub contains 3 4-byte instructions, aligned at 4 bytes. See
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// emitFunctionStub for details.
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StubLayout Result = { 3*4, 4 };
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// The stub contains maximum of 4 4-byte instructions and 8 bytes for address,
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// aligned at 32 bytes.
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// See emitFunctionStub and emitInstrForIndirectJump for details.
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StubLayout Result = { 4*4 + 8, 32 };
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return Result;
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}
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void *SparcJITInfo::emitFunctionStub(const Function *F, void *Fn,
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JITCodeEmitter &JCE)
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{
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JCE.emitAlignment(4);
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JCE.emitAlignment(32);
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void *Addr = (void*) (JCE.getCurrentPCValue());
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if (!sys::Memory::setRangeWritable(Addr, 12))
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intptr_t CurrentAddr = (intptr_t)Addr;
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intptr_t EmittedAddr;
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SmallVector<uint32_t, 8> Insts;
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if (Fn != (void*)(intptr_t)SparcCompilationCallback) {
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EmittedAddr = (intptr_t)Fn;
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intptr_t diff = (EmittedAddr - CurrentAddr) >> 2;
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if (isInt<22>(diff)) {
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Insts.push_back(BA_INST(diff));
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Insts.push_back(NOP_INST);
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}
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} else {
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EmittedAddr = (intptr_t)SparcCompilationCallback;
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}
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if (Insts.size() == 0)
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emitInstrForIndirectJump(EmittedAddr, 1, Insts);
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if (!sys::Memory::setRangeWritable(Addr, 4 * Insts.size()))
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llvm_unreachable("ERROR: Unable to mark stub writable.");
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intptr_t EmittedAddr;
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if (Fn != (void*)(intptr_t)SparcCompilationCallback)
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EmittedAddr = (intptr_t)Fn;
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else
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EmittedAddr = (intptr_t)SparcCompilationCallback;
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for (unsigned i = 0, e = Insts.size(); i != e; ++i)
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JCE.emitWordBE(Insts[i]);
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// sethi %hi(EmittedAddr), %g1
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// jmp %g1+%lo(EmittedAddr), %g1
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// nop
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JCE.emitWordBE(SETHI_INST(HI(EmittedAddr), 1));
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JCE.emitWordBE(JMP_INST(1, LO(EmittedAddr), 1));
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JCE.emitWordBE(NOP_INST);
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sys::Memory::InvalidateInstructionCache(Addr, 12);
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if (!sys::Memory::setRangeExecutable(Addr, 12))
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sys::Memory::InvalidateInstructionCache(Addr, 4 * Insts.size());
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if (!sys::Memory::setRangeExecutable(Addr, 4 * Insts.size()))
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llvm_unreachable("ERROR: Unable to mark stub executable.");
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return Addr;
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}
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TargetJITInfo::LazyResolverFn
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SparcJITInfo::getLazyResolverFunction(JITCompilerFn F) {
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JITCompilerFunction = F;
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@ -158,6 +255,27 @@ void SparcJITInfo::relocate(void *Function, MachineRelocation *MR,
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case SP::reloc_sparc_pc19:
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ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x7ffff;
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break;
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case SP::reloc_sparc_h44:
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ResultPtr = (ResultPtr >> 22) & 0x3fffff;
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break;
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case SP::reloc_sparc_m44:
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ResultPtr = (ResultPtr >> 12) & 0x3ff;
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break;
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case SP::reloc_sparc_l44:
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ResultPtr = (ResultPtr & 0xfff);
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break;
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case SP::reloc_sparc_hh:
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ResultPtr = (((int64_t)ResultPtr) >> 42) & 0x3fffff;
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break;
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case SP::reloc_sparc_hm:
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ResultPtr = (((int64_t)ResultPtr) >> 32) & 0x3ff;
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break;
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}
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*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
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}
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@ -33,7 +33,22 @@ namespace llvm {
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reloc_sparc_pc22 = 4,
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// reloc_sparc_pc22 - pc rel. 19 bits for branch with icc/xcc
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reloc_sparc_pc19 = 5
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reloc_sparc_pc19 = 5,
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// reloc_sparc_h44 - 43-22 bits
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reloc_sparc_h44 = 6,
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// reloc_sparc_m44 - 21-12 bits
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reloc_sparc_m44 = 7,
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// reloc_sparc_l44 - lower 12 bits
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reloc_sparc_l44 = 8,
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// reloc_sparc_hh - 63-42 bits
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reloc_sparc_hh = 9,
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// reloc_sparc_hm - 41-32 bits
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reloc_sparc_hm = 10
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};
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}
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}
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