replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

X86: Don't form min/max nodes if the target is missing SSE. 

llvm-svn: 140294
This commit is contained in:
Benjamin Kramer 2011-09-22 03:01:42 +00:00
parent 751c558d8e
commit dc397a6402
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -12568,7 +12568,8 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
// instructions match the semantics of the common C idiom x<y?x:y but not
// x<=y?x:y, because of how they handle negative zero (which can be
// ignored in unsafe-math mode).
if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
if (Subtarget->hasXMM() &&
Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();