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bpf: add variants of -mcpu=# and support for additional jmp insns 

-mcpu=# will support:
  . generic: the default insn set
  . v1: insn set version 1, the same as generic
  . v2: insn set version 2, version 1 + additional jmp insns
  . probe: the compiler will probe the underlying kernel to
           decide proper version of insn set.

We did not not use -mcpu=native since llc/llvm will interpret -mcpu=native
as the underlying hardware architecture regardless of -march value.

Currently, only x86_64 supports -mcpu=probe. Other architecture will
silently revert to "generic".

Also added -mcpu=help to print available cpu parameters.
llvm will print out the information only if there are at least one
cpu and at least one feature. Add an unused dummy feature to
enable the printout.

Examples for usage:
$ llc -march=bpf -mcpu=v1 -filetype=asm t.ll
$ llc -march=bpf -mcpu=v2 -filetype=asm t.ll
$ llc -march=bpf -mcpu=generic -filetype=asm t.ll
$ llc -march=bpf -mcpu=probe -filetype=asm t.ll
$ llc -march=bpf -mcpu=v3 -filetype=asm t.ll
'v3' is not a recognized processor for this target (ignoring processor)
...
$ llc -march=bpf -mcpu=help -filetype=asm t.ll
Available CPUs for this target:

  generic - Select the generic processor.
  probe   - Select the probe processor.
  v1      - Select the v1 processor.
  v2      - Select the v2 processor.

Available features for this target:

  dummy - unused feature.

Use +feature to enable a feature, or -feature to disable it.
For example, llc -mcpu=mycpu -mattr=+feature1,-feature2
...

Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Signed-off-by: Yonghong Song <yhs@fb.com>
Acked-by: Alexei Starovoitov <ast@kernel.org>
llvm-svn: 311522
This commit is contained in:
Yonghong Song 2017-08-23 04:25:57 +00:00
parent d6c0868da5
commit dc1dbf6ef3
9 changed files with 147 additions and 17 deletions
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1
llvm/include/llvm/Support/Host.h
View File

@ -92,6 +92,7 @@ constexpr bool IsBigEndianHost = false;
StringRef getHostCPUNameForPowerPC(const StringRef &ProcCpuinfoContent);
StringRef getHostCPUNameForARM(const StringRef &ProcCpuinfoContent);
StringRef getHostCPUNameForS390x(const StringRef &ProcCpuinfoContent);
StringRef getHostCPUNameForBPF();
}
}
}

39
llvm/lib/Support/Host.cpp
View File

@ -267,6 +267,43 @@ StringRef sys::detail::getHostCPUNameForS390x(
return "generic";
}
StringRef sys::detail::getHostCPUNameForBPF() {
#if !defined(__linux__) || !defined(__x86_64__)
return "generic";
#else
uint8_t insns[40] __attribute__ ((aligned (8))) =
/* BPF_MOV64_IMM(BPF_REG_0, 0) */
{ 0xb7, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
/* BPF_MOV64_IMM(BPF_REG_2, 1) */
0xb7, 0x2, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
/* BPF_JMP_REG(BPF_JLT, BPF_REG_0, BPF_REG_2, 1) */
0xad, 0x20, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0,
/* BPF_MOV64_IMM(BPF_REG_0, 1) */
0xb7, 0x0, 0x0, 0x0, 0x1, 0x0, 0x0, 0x0,
/* BPF_EXIT_INSN() */
0x95, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
struct bpf_prog_load_attr {
uint32_t prog_type;
uint32_t insn_cnt;
uint64_t insns;
uint64_t license;
uint32_t log_level;
uint32_t log_size;
uint64_t log_buf;
uint32_t kern_version;
uint32_t prog_flags;
} attr = {};
attr.prog_type = 1; /* BPF_PROG_TYPE_SOCKET_FILTER */
attr.insn_cnt = 5;
attr.insns = (uint64_t)insns;
attr.license = (uint64_t)"DUMMY";
int fd = syscall(321 /* __NR_bpf */, 5 /* BPF_PROG_LOAD */, &attr, sizeof(attr));
return (fd > 0) ? "v2" : "v1";
#endif
}
#if defined(__i386__) || defined(_M_IX86) || \
defined(__x86_64__) || defined(_M_X64)
@ -1420,7 +1457,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["prefetchwt1"] = HasLeaf7 && (ECX & 1);
Features["avx512vbmi"] = HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save;
Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
// Enable protection keys
Features["pku"] = HasLeaf7 && ((ECX >> 4) & 1);

6
llvm/lib/Target/BPF/BPF.td
View File

@ -19,6 +19,12 @@ class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Proc<"generic", []>;
def : Proc<"v1", []>;
def : Proc<"v2", []>;
def : Proc<"probe", []>;
def DummyFeature : SubtargetFeature<"dummy", "isDummyMode",
"true", "unused feature">;
def BPFInstPrinter : AsmWriter {
string AsmWriterClassName = "InstPrinter";

21
llvm/lib/Target/BPF/BPFISelLowering.cpp
View File

@ -130,6 +130,9 @@ BPFTargetLowering::BPFTargetLowering(const TargetMachine &TM,
MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 128;
MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 128;
MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize = 128;
// CPU/Feature control
HasJmpExt = STI.getHasJmpExt();
}
bool BPFTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
@ -456,7 +459,8 @@ SDValue BPFTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue Dest = Op.getOperand(4);
SDLoc DL(Op);
NegateCC(LHS, RHS, CC);
if (!getHasJmpExt())
NegateCC(LHS, RHS, CC);
return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS,
DAG.getConstant(CC, DL, MVT::i64), Dest);
@ -470,7 +474,8 @@ SDValue BPFTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
SDLoc DL(Op);
NegateCC(LHS, RHS, CC);
if (!getHasJmpExt())
NegateCC(LHS, RHS, CC);
SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i64);
@ -570,6 +575,18 @@ BPFTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case ISD::SETNE:
NewCC = isSelectOp ? BPF::JNE_rr : BPF::JNE_ri;
break;
case ISD::SETLT:
NewCC = isSelectOp ? BPF::JSLT_rr : BPF::JSLT_ri;
break;
case ISD::SETULT:
NewCC = isSelectOp ? BPF::JULT_rr : BPF::JULT_ri;
break;
case ISD::SETLE:
NewCC = isSelectOp ? BPF::JSLE_rr : BPF::JSLE_ri;
break;
case ISD::SETULE:
NewCC = isSelectOp ? BPF::JULE_rr : BPF::JULE_ri;
break;
default:
report_fatal_error("unimplemented select CondCode " + Twine(CC));
}

5
llvm/lib/Target/BPF/BPFISelLowering.h
View File

@ -50,7 +50,12 @@ public:
EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const override;
bool getHasJmpExt() const { return HasJmpExt; }
private:
// Control Instruction Selection Features
bool HasJmpExt;
SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;

12
llvm/lib/Target/BPF/BPFInstrInfo.td
View File

@ -79,6 +79,14 @@ def BPF_CC_GTU : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETUGT);}]>;
def BPF_CC_GEU : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETUGE);}]>;
def BPF_CC_LE : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETLE);}]>;
def BPF_CC_LT : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETLT);}]>;
def BPF_CC_LTU : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETULT);}]>;
def BPF_CC_LEU : PatLeaf<(i64 imm),
[{return (N->getZExtValue() == ISD::SETULE);}]>;
// jump instructions
class JMP_RR<bits<4> Opc, string OpcodeStr, PatLeaf Cond>
@ -136,6 +144,10 @@ defm JUGE : J<0x3, ">=", BPF_CC_GEU>;
defm JNE : J<0x5, "!=", BPF_CC_NE>;
defm JSGT : J<0x6, "s>", BPF_CC_GT>;
defm JSGE : J<0x7, "s>=", BPF_CC_GE>;
defm JULT : J<0xa, "<", BPF_CC_LTU>;
defm JULE : J<0xb, "<=", BPF_CC_LEU>;
defm JSLT : J<0xc, "s<", BPF_CC_LT>;
defm JSLE : J<0xd, "s<=", BPF_CC_LE>;
}
// ALU instructions

26
llvm/lib/Target/BPF/BPFSubtarget.cpp
View File

@ -13,6 +13,7 @@
#include "BPFSubtarget.h"
#include "BPF.h"
#include "llvm/Support/Host.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
@ -25,7 +26,30 @@ using namespace llvm;
void BPFSubtarget::anchor() {}
BPFSubtarget &BPFSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
initializeEnvironment();
initSubtargetFeatures(CPU, FS);
return *this;
}
void BPFSubtarget::initializeEnvironment() {
HasJmpExt = false;
}
void BPFSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
if (CPU == "probe")
CPU = sys::detail::getHostCPUNameForBPF();
if (CPU == "generic" || CPU == "v1")
return;
if (CPU == "v2") {
HasJmpExt = true;
return;
}
}
BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS, const TargetMachine &TM)
: BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this),
: BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(),
FrameLowering(initializeSubtargetDependencies(CPU, FS)),
TLInfo(TM, *this) {}

15
llvm/lib/Target/BPF/BPFSubtarget.h
View File

@ -35,15 +35,30 @@ class BPFSubtarget : public BPFGenSubtargetInfo {
BPFTargetLowering TLInfo;
SelectionDAGTargetInfo TSInfo;
private:
void initializeEnvironment();
void initSubtargetFeatures(StringRef CPU, StringRef FS);
bool probeJmpExt();
protected:
// unused
bool isDummyMode;
// whether the cpu supports jmp ext
bool HasJmpExt;
public:
// This constructor initializes the data members to match that
// of the specified triple.
BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
const TargetMachine &TM);
BPFSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options. Definition of function is auto generated by tblgen.
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
bool getHasJmpExt() const { return HasJmpExt; }
const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const BPFFrameLowering *getFrameLowering() const override {

39
llvm/test/CodeGen/BPF/setcc.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -march=bpfel < %s | FileCheck %s
; RUN: llc -march=bpfel < %s | FileCheck --check-prefix=CHECK-V1 %s
; RUN: llc -march=bpfel -mcpu=v2 < %s | FileCheck --check-prefix=CHECK-V2 %s
define i16 @sccweqand(i16 %a, i16 %b) nounwind {
%t1 = and i16 %a, %b
@ -7,7 +8,8 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind {
ret i16 %t3
}
; CHECK-LABEL: sccweqand:
; CHECK: if r1 == 0
; CHECK-V1: if r1 == 0
; CHECK-V2: if r1 == 0
define i16 @sccwneand(i16 %a, i16 %b) nounwind {
%t1 = and i16 %a, %b
@ -16,7 +18,8 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind {
ret i16 %t3
}
; CHECK-LABEL: sccwneand:
; CHECK: if r1 != 0
; CHECK-V1: if r1 != 0
; CHECK-V2: if r1 != 0
define i16 @sccwne(i16 %a, i16 %b) nounwind {
%t1 = icmp ne i16 %a, %b
@ -24,7 +27,8 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwne:
; CHECK: if r1 != r2
; CHECK-V1: if r1 != r2
; CHECK-V2: if r1 != r2
define i16 @sccweq(i16 %a, i16 %b) nounwind {
%t1 = icmp eq i16 %a, %b
@ -32,7 +36,8 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccweq:
; CHECK: if r1 == r2
; CHECK-V1: if r1 == r2
; CHECK-V2: if r1 == r2
define i16 @sccwugt(i16 %a, i16 %b) nounwind {
%t1 = icmp ugt i16 %a, %b
@ -40,7 +45,8 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwugt:
; CHECK: if r1 > r2
; CHECK-V1: if r1 > r2
; CHECK-V2: if r1 > r2
define i16 @sccwuge(i16 %a, i16 %b) nounwind {
%t1 = icmp uge i16 %a, %b
@ -48,7 +54,8 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwuge:
; CHECK: if r1 >= r2
; CHECK-V1: if r1 >= r2
; CHECK-V2: if r1 >= r2
define i16 @sccwult(i16 %a, i16 %b) nounwind {
%t1 = icmp ult i16 %a, %b
@ -56,7 +63,8 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwult:
; CHECK: if r2 > r1
; CHECK-V1: if r2 > r1
; CHECK-V2: if r1 < r2
define i16 @sccwule(i16 %a, i16 %b) nounwind {
%t1 = icmp ule i16 %a, %b
@ -64,7 +72,8 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwule:
; CHECK: if r2 >= r1
; CHECK-V1: if r2 >= r1
; CHECK-V2: if r1 <= r2
define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
%t1 = icmp sgt i16 %a, %b
@ -72,7 +81,8 @@ define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwsgt:
; CHECK: if r1 s> r2
; CHECK-V1: if r1 s> r2
; CHECK-V2: if r1 s> r2
define i16 @sccwsge(i16 %a, i16 %b) nounwind {
%t1 = icmp sge i16 %a, %b
@ -80,7 +90,8 @@ define i16 @sccwsge(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwsge:
; CHECK: if r1 s>= r2
; CHECK-V1: if r1 s>= r2
; CHECK-V2: if r1 s>= r2
define i16 @sccwslt(i16 %a, i16 %b) nounwind {
%t1 = icmp slt i16 %a, %b
@ -88,7 +99,8 @@ define i16 @sccwslt(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwslt:
; CHECK: if r2 s> r1
; CHECK-V1: if r2 s> r1
; CHECK-V2: if r1 s< r2
define i16 @sccwsle(i16 %a, i16 %b) nounwind {
%t1 = icmp sle i16 %a, %b
@ -96,4 +108,5 @@ define i16 @sccwsle(i16 %a, i16 %b) nounwind {
ret i16 %t2
}
; CHECK-LABEL:sccwsle:
; CHECK: if r2 s>= r1
; CHECK-V1: if r2 s>= r1
; CHECK-V2: if r1 s<= r2