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R600/SI: Prettier operand printing for 64-bit ops. 

Copy what is done for 32-bit already so the order is about the same.

llvm-svn: 211186
This commit is contained in:
Matt Arsenault 2014-06-18 17:13:51 +00:00
parent 784f797d4c
commit dbc9aae1fb
3 changed files with 20 additions and 18 deletions
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23
llvm/lib/Target/R600/SIISelLowering.cpp
View File

@ -485,19 +485,20 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MI->eraseFromParent();
break;
}
case AMDGPU::V_SUB_F64:
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addReg(MI->getOperand(2).getReg())
.addImm(0) /* src2 */
.addImm(0) /* ABS */
.addImm(0) /* CLAMP */
.addImm(0) /* OMOD */
.addImm(2); /* NEG */
case AMDGPU::V_SUB_F64: {
unsigned DestReg = MI->getOperand(0).getReg();
BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::V_ADD_F64), DestReg)
.addImm(0) // SRC0 modifiers
.addReg(MI->getOperand(1).getReg())
.addImm(1) // SRC1 modifiers
.addReg(MI->getOperand(2).getReg())
.addImm(0) // SRC2 modifiers
.addImm(0) // src2
.addImm(0) // CLAMP
.addImm(0); // OMOD
MI->eraseFromParent();
break;
}
case AMDGPU::SI_RegisterStorePseudo: {
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
unsigned Reg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);

8
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -426,9 +426,11 @@ class VOP3_64_32 <bits <9> op, string opName, list<dag> pattern> : VOP3 <
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
op, (outs VReg_64:$dst),
(ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg),
opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
(ins InputMods:$src0_modifiers, VSrc_64:$src0,
InputMods:$src1_modifiers, VSrc_64:$src1,
InputMods:$src2_modifiers, VSrc_64:$src2,
InstFlag:$clamp, InstFlag:$omod),
opName#" $dst, $src0_modifiers, $src1_modifiers, $src2_modifiers, $clamp, $omod", pattern
>, VOP <opName>;
//===----------------------------------------------------------------------===//

7
llvm/test/CodeGen/R600/fsub64.ll
View File

@ -1,8 +1,7 @@
; RUN: llc < %s -march=r600 -mcpu=tahiti -verify-machineinstrs | FileCheck %s
; CHECK: @fsub_f64
; CHECK: V_ADD_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}, 0, 0, 0, 0, 2
; RUN: llc -march=r600 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; SI-LABEL: @fsub_f64:
; SI: V_ADD_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
define void @fsub_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
double addrspace(1)* %in2) {
%r0 = load double addrspace(1)* %in1