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Fix some broken CHECK lines. 

The colon is important.

llvm-svn: 292761
This commit is contained in:
Benjamin Kramer 2017-01-22 20:28:56 +00:00
parent e5f6daa475
commit db9e0b659d
28 changed files with 54 additions and 54 deletions
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2
llvm/test/Analysis/DivergenceAnalysis/AMDGPU/kernel-args.ll
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@ -3,7 +3,7 @@
; CHECK: DIVERGENT: ; CHECK: DIVERGENT:
; CHECK-NOT: %arg0 ; CHECK-NOT: %arg0
; CHECK-NOT: %arg1 ; CHECK-NOT: %arg1
; CHECK-NOT; %arg2 ; CHECK-NOT: %arg2
; CHECK: <2 x i32> %arg3 ; CHECK: <2 x i32> %arg3
; CHECK: DIVERGENT: <3 x i32> %arg4 ; CHECK: DIVERGENT: <3 x i32> %arg4
; CHECK: DIVERGENT: float %arg5 ; CHECK: DIVERGENT: float %arg5

12
llvm/test/Analysis/ScalarEvolution/incorrect-offset-scaling.ll
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@ -36,13 +36,13 @@ ib: ; preds = %if6
%r4 = mul i64 %r3, %r0 %r4 = mul i64 %r3, %r0
%r5 = add i64 %r2, %r4 %r5 = add i64 %r2, %r4
%r6 = icmp ult i64 %r5, undef %r6 = icmp ult i64 %r5, undef
; CHECK %2 = mul i64 %lsr.iv, %r3 ; CHECK: %2 = mul i64 %lsr.iv, %r3
; CHECK %3 = add i64 %1, -1 ; CHECK: %3 = add i64 %2, -1
; CHECK %4 = add i64 %0, %r3 ; CHECK: %4 = add i64 %0, %3
; CHECK %r6 ; CHECK: %r6
%r7 = getelementptr i64, i64* undef, i64 %r5 %r7 = getelementptr i64, i64* undef, i64 %r5
store i64 1, i64* %r7, align 8 store i64 1, i64* %r7, align 8
; CHECK %5 = mul i64 %lsr.iv, %r3 ; CHECK: %5 = mul i64 %lsr.iv, %r3
; CHECK %6 = add i64 %5, -1 ; CHECK: %6 = add i64 %5, -1
br label %L br label %L
} }

2
llvm/test/CodeGen/AArch64/GlobalISel/legalize-constant.mir
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@ -57,7 +57,7 @@ body: |
; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00 ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
; CHECK: %1(s64) = G_FCONSTANT double 2.000000e+00 ; CHECK: %1(s64) = G_FCONSTANT double 2.000000e+00
; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000 ; CHECK: [[TMP:%[0-9]+]](s32) = G_FCONSTANT half 0xH0000
; CHECK; %2(s16) = G_FPTRUNC [[TMP]] ; CHECK: %2(s16) = G_FPTRUNC [[TMP]]
%0(s32) = G_FCONSTANT float 1.0 %0(s32) = G_FCONSTANT float 1.0
%1(s64) = G_FCONSTANT double 2.0 %1(s64) = G_FCONSTANT double 2.0

4
llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
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@ -236,14 +236,14 @@ define void @test_zero_reg(i32* %addr) {
define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind { define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind {
; CHECK-LABEL: test_vreg_64bit: ; CHECK-LABEL: test_vreg_64bit:
%1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind %1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind
; CHECK fadd v14.2s, v0.2s, v0.2s: ; CHECK: fadd v14.2s, v0.2s, v0.2s
ret <2 x float> %1 ret <2 x float> %1
} }
define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind { define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind {
; CHECK-LABEL: test_vreg_128bit: ; CHECK-LABEL: test_vreg_128bit:
%1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind %1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind
; CHECK fadd v14.4s, v0.4s, v0.4s: ; CHECK: fadd v14.4s, v0.4s, v0.4s
ret <4 x float> %1 ret <4 x float> %1
} }

2
llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
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@ -28,7 +28,7 @@ define i64 @test_chains() {
; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]] ; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1
; CHECK: sturb w[[STRVAL:[0-9]+]], [x29, [[LOCADDR]]] ; CHECK: sturb w[[STRVAL:[0-9]+]], [x29, [[LOCADDR]]]
; CHECK; and w0, w[[STRVAL]], #0xff ; CHECK: and w0, w[[STRVAL]], #0xff
%ret.1 = load i8, i8* %locvar %ret.1 = load i8, i8* %locvar
%ret.2 = zext i8 %ret.1 to i64 %ret.2 = zext i8 %ret.1 to i64

2
llvm/test/CodeGen/AMDGPU/gv-offset-folding.ll
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@ -12,7 +12,7 @@
; for local memory globals. ; for local memory globals.
; CHECK-LABEL: lds_no_offset: ; CHECK-LABEL: lds_no_offset:
; CHECK ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:4 ; CHECK: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:4
define void @lds_no_offset() { define void @lds_no_offset() {
entry: entry:
%ptr = getelementptr [4 x i32], [4 x i32] addrspace(3)* @lds, i32 0, i32 1 %ptr = getelementptr [4 x i32], [4 x i32] addrspace(3)* @lds, i32 0, i32 1

4
llvm/test/CodeGen/AMDGPU/promote-alloca-volatile.ll
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@ -2,7 +2,7 @@
; CHECK-LABEL: @volatile_load( ; CHECK-LABEL: @volatile_load(
; CHECK: alloca [5 x i32] ; CHECK: alloca [5 x i32]
; CHECK load volatile i32, i32* ; CHECK: load volatile i32, i32*
define void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { define void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4
@ -15,7 +15,7 @@ entry:
; CHECK-LABEL: @volatile_store( ; CHECK-LABEL: @volatile_store(
; CHECK: alloca [5 x i32] ; CHECK: alloca [5 x i32]
; CHECK store volatile i32 %tmp, i32* ; CHECK: store volatile i32 %tmp, i32*
define void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { define void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4

4
llvm/test/CodeGen/Mips/compactbranches/compact-branches.ll
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@ -38,7 +38,7 @@ entry:
; PIC: jalrc $25 ; PIC: jalrc $25
%call1 = tail call i32 @i() %call1 = tail call i32 @i()
%cmp = icmp eq i32 %call, %call1 %cmp = icmp eq i32 %call, %call1
; CHECK beqc ; CHECK: beqc
br i1 %cmp, label %if.end, label %if.then br i1 %cmp, label %if.end, label %if.then
if.then: ; preds = %entry: if.then: ; preds = %entry:
@ -61,7 +61,7 @@ entry:
; PIC: jalrc $25 ; PIC: jalrc $25
%call = tail call i32 @k() %call = tail call i32 @k()
%cmp = icmp slt i32 %call, 0 %cmp = icmp slt i32 %call, 0
; CHECK : bgez ; CHECK: bgez
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry: if.then: ; preds = %entry:

2
llvm/test/CodeGen/NVPTX/intrinsics.ll
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@ -24,7 +24,7 @@ define float @test_nvvm_sqrt(float %a) {
; CHECK-LABEL: test_llvm_sqrt( ; CHECK-LABEL: test_llvm_sqrt(
define float @test_llvm_sqrt(float %a) { define float @test_llvm_sqrt(float %a) {
; CHECK sqrt.rn.f32 ; CHECK: sqrt.rn.f32
%val = call float @llvm.sqrt.f32(float %a) %val = call float @llvm.sqrt.f32(float %a)
ret float %val ret float %val
} }

2
llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
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@ -403,7 +403,7 @@ entry:
; CHECK: [[ELSE_LABEL]] ; CHECK: [[ELSE_LABEL]]
; CHECK-NEXT: slwi 3, 4, 1 ; CHECK-NEXT: slwi 3, 4, 1
; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload ; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
; CHECK-NEXT blr ; CHECK-NEXT: blr
; ;
define i32 @inlineAsm(i32 %cond, i32 %N) { define i32 @inlineAsm(i32 %cond, i32 %N) {
entry: entry:

4
llvm/test/CodeGen/PowerPC/vec_absd.ll
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@ -18,7 +18,7 @@ entry:
ret <16 x i8> %res ret <16 x i8> %res
; CHECK-LABEL: @test_byte ; CHECK-LABEL: @test_byte
; CHECK: vabsdub 2, 2, 3 ; CHECK: vabsdub 2, 2, 3
; CHECK blr ; CHECK: blr
} }
define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @test_half(<8 x i16> %a, <8 x i16> %b) {
@ -27,7 +27,7 @@ entry:
ret <8 x i16> %res ret <8 x i16> %res
; CHECK-LABEL: @test_half ; CHECK-LABEL: @test_half
; CHECK: vabsduh 2, 2, 3 ; CHECK: vabsduh 2, 2, 3
; CHECK blr ; CHECK: blr
} }
define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @test_word(<4 x i32> %a, <4 x i32> %b) {

12
llvm/test/CodeGen/PowerPC/vsx-p9.ll
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@ -277,8 +277,8 @@ entry:
%0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a) %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxexpdp(<2 x double> %a)
ret <2 x i64> %0 ret <2 x i64> %0
; CHECK-LABEL: testXVXEXPDP ; CHECK-LABEL: testXVXEXPDP
; CHECK xvxexpdp 34, 34 ; CHECK: xvxexpdp 34, 34
; CHECK blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>) declare <2 x i64>@llvm.ppc.vsx.xvxexpdp(<2 x double>)
@ -289,8 +289,8 @@ entry:
%0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a) %0 = tail call <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float> %a)
ret <4 x i32> %0 ret <4 x i32> %0
; CHECK-LABEL: testXVXSIGSP ; CHECK-LABEL: testXVXSIGSP
; CHECK xvxsigsp 34, 34 ; CHECK: xvxsigsp 34, 34
; CHECK blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>) declare <4 x i32> @llvm.ppc.vsx.xvxsigsp(<4 x float>)
@ -301,8 +301,8 @@ entry:
%0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a) %0 = tail call <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double> %a)
ret <2 x i64> %0 ret <2 x i64> %0
; CHECK-LABEL: testXVXSIGDP ; CHECK-LABEL: testXVXSIGDP
; CHECK xvxsigdp 34, 34 ; CHECK: xvxsigdp 34, 34
; CHECK blr ; CHECK: blr
} }
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>) declare <2 x i64> @llvm.ppc.vsx.xvxsigdp(<2 x double>)

2
llvm/test/CodeGen/X86/select_meta.ll
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@ -13,4 +13,4 @@ define i32 @foo(i32, i32, i32) {
!0 = !{!"clang version 4.0.0 (trunk 279683)"} !0 = !{!"clang version 4.0.0 (trunk 279683)"}
!1 = !{!"branch_weights", i32 1000, i32 1 } !1 = !{!"branch_weights", i32 1000, i32 1 }
; CHECK ![[WT]] = !{!"branch_weights", i32 1000, i32 1 } ; CHECK: ![[WT]] = !{!"branch_weights", i32 1000, i32 1}

2
llvm/test/CodeGen/X86/tail-merge-unreachable.ll
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@ -29,6 +29,6 @@ end:
; CHECK: [[JUMP_TABLE_BLOCK]]: ; CHECK: [[JUMP_TABLE_BLOCK]]:
; CHECK: btl ; CHECK: btl
; CHECK: jae [[UNREACHABLE_BLOCK:[.][A-Za-z0-9_]+]] ; CHECK: jae [[UNREACHABLE_BLOCK:[.][A-Za-z0-9_]+]]
; CHECK [[UNREACHABLE_BLOCK]]: ; CHECK: [[UNREACHABLE_BLOCK]]:
; CHECK: .Lfunc_end0 ; CHECK: .Lfunc_end0
} }

2
llvm/test/CodeGen/X86/unreachableblockelim.ll
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@ -7,7 +7,7 @@ target triple = "x86_64-unknown-linux-gnu"
declare void @abort() declare void @abort()
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NOT return: ; CHECK-NOT: return:
define void @foo(i32* %p) { define void @foo(i32* %p) {
entry: entry:
%p.addr = alloca i32*, align 8 %p.addr = alloca i32*, align 8

2
llvm/test/CodeGen/X86/x86-sanitizer-shrink-wrapping.ll
View File

@ -12,7 +12,7 @@ target triple = "x86_64-apple-macosx"
; CHECK: popq ; CHECK: popq
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; CHECK: movl $40, %edi ; CHECK: movl $40, %edi
; CHECK-NEXT callq ___asan_report_load4 ; CHECK-NEXT: callq ___asan_report_load4
define void @sanitize() #0 { define void @sanitize() #0 {
entry: entry:
%tmp = load i8, i8* inttoptr (i64 17592186044421 to i8*) %tmp = load i8, i8* inttoptr (i64 17592186044421 to i8*)

2
llvm/test/Feature/OperandBundles/dse.ll
View File

@ -39,7 +39,7 @@ define void @test_2() {
ret void ret void
; CHECK: tail call void @f() [ "deopt"(i8* %m) ] ; CHECK: tail call void @f() [ "deopt"(i8* %m) ]
; CHECK-NEXT ret void ; CHECK-NEXT: ret void
} }
define i8* @test_3() { define i8* @test_3() {

2
llvm/test/MC/AArch64/neon-add-sub-instructions.s
View File

@ -67,7 +67,7 @@
fsub v0.2d, v1.2d, v2.2d fsub v0.2d, v1.2d, v2.2d
// CHECK: fsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0xc2,0x0e] // CHECK: fsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0xc2,0x0e]
// CHECK; fsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0xc2,0x4e] // CHECK: fsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0xc2,0x4e]
// CHECK: fsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x0e] // CHECK: fsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x0e]
// CHECK: fsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0xa2,0x4e] // CHECK: fsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0xa2,0x4e]
// CHECK: fsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0xe2,0x4e] // CHECK: fsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0xe2,0x4e]

2
llvm/test/MC/ARM/ldr-pseudo-cond-darwin.s
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@ -37,7 +37,7 @@ f2:
@ CHECK-ARM moveq r2, #520093696 @ CHECK-ARM moveq r2, #520093696
@ CHECK-THUMB2 moveq.w r2, #520093696 @ CHECK-THUMB2 moveq.w r2, #520093696
ldrne r3, = 0x00001234 ldrne r3, = 0x00001234
@ CHECK movwne r2, #4660 @ CHECK: movwne r3, #4660
@ @
@ Constant Pools @ Constant Pools

2
llvm/test/MC/ARM/ldr-pseudo-cond.s
View File

@ -37,7 +37,7 @@ f2:
@ CHECK-ARM moveq r2, #520093696 @ CHECK-ARM moveq r2, #520093696
@ CHECK-THUMB2 moveq.w r2, #520093696 @ CHECK-THUMB2 moveq.w r2, #520093696
ldrne r3, = 0x00001234 ldrne r3, = 0x00001234
@ CHECK movwne r2, #4660 @ CHECK: movwne r3, #4660
@ @
@ Constant Pools @ Constant Pools

2
llvm/test/MC/Mips/macro-li.s
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@ -65,7 +65,7 @@ li $5, 0xc0008000 # CHECK: lui $5, 49152 # encoding: [0x3c,0x05,0xc0,0x00
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00] li $5, 0x80008000 # CHECK: lui $5, 32768 # encoding: [0x3c,0x05,0x80,0x00]
# CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00] # CHECK: ori $5, $5, 32768 # encoding: [0x34,0xa5,0x80,0x00]
li $4, ~0xffffffff # CHECK; addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00] li $4, ~0xffffffff # CHECK: addiu $4, $zero, 0 # encoding: [0x24,0x04,0x00,0x00]
li $4, ~0x80000001 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff] li $4, ~0x80000001 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff]
# CHECK: ori $4, $4, 65534 # encoding: [0x34,0x84,0xff,0xfe] # CHECK: ori $4, $4, 65534 # encoding: [0x34,0x84,0xff,0xfe]
li $4, ~0x80000000 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff] li $4, ~0x80000000 # CHECK: lui $4, 32767 # encoding: [0x3c,0x04,0x7f,0xff]

8
llvm/test/MC/Mips/micromips32r6/valid.s
View File

@ -100,10 +100,10 @@
syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c] syscall 396 # CHECK: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]
mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58] mod $3, $4, $5 # CHECK: mod $3, $4, $5 # encoding: [0x00,0xa4,0x19,0x58]
modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8] modu $3, $4, $5 # CHECK: modu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd8]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] mul $3, $4, $5 # CHECK: mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] muh $3, $4, $5 # CHECK: muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] mulu $3, $4, $5 # CHECK: mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00] nop # CHECK: nop # encoding: [0x00,0x00,0x00,0x00]
nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0] nor $3, $4, $5 # CHECK: nor $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0xd0]
or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90] or $3, $4, $5 # CHECK: or $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x90]

16
llvm/test/MC/Mips/micromips64r6/valid.s
View File

@ -269,14 +269,14 @@ a:
dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90] dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90]
dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0] dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0]
dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0] dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0]
mul $3, $4, $5 # CHECK mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18] mul $3, $4, $5 # CHECK: mul $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x18]
muh $3, $4, $5 # CHECK muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58] muh $3, $4, $5 # CHECK: muh $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x58]
mulu $3, $4, $5 # CHECK mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98] mulu $3, $4, $5 # CHECK: mulu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0x98]
muhu $3, $4, $5 # CHECK muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8] muhu $3, $4, $5 # CHECK: muhu $3, $4, $5 # encoding: [0x00,0xa4,0x18,0xd8]
dmul $3, $4, $5 # CHECK dmul $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x18] dmul $3, $4, $5 # CHECK: dmul $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x18]
dmuh $3, $4, $5 # CHECK dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58] dmuh $3, $4, $5 # CHECK: dmuh $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x58]
dmulu $3, $4, $5 # CHECK dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98] dmulu $3, $4, $5 # CHECK: dmulu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0x98]
dmuhu $3, $4, $5 # CHECK dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8] dmuhu $3, $4, $5 # CHECK: dmuhu $3, $4, $5 # encoding: [0x58,0xa4,0x18,0xd8]
lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] lwp $16, 8($4) # CHECK: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08]
swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] swp $16, 8($4) # CHECK: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08]
dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c] dsbh $3, $4 # CHECK: dsbh $3, $4 # encoding: [0x58,0x64,0x7b,0x3c]

4
llvm/test/Transforms/GlobalOpt/externally-initialized-aggregate.ll
View File

@ -5,11 +5,11 @@
; store to @a[0] from being constant propagated to the load in @foo, but will not ; store to @a[0] from being constant propagated to the load in @foo, but will not
; prevent @a[1] from being removed since it is dead. ; prevent @a[1] from being removed since it is dead.
; CHECK: @a.0 = internal unnamed_addr externally_initialized global i32 undef ; CHECK: @a.0 = internal unnamed_addr externally_initialized global i32 undef
; CHECK-NOT @a.1 ; CHECK-NOT: @a.1
@a = internal externally_initialized global [2 x i32] undef, align 4 @a = internal externally_initialized global [2 x i32] undef, align 4
; This is the same, but a struct rather than an array. ; This is the same, but a struct rather than an array.
; CHECK: @b.0 = internal unnamed_addr externally_initialized global i32 undef ; CHECK: @b.0 = internal unnamed_addr externally_initialized global i32 undef
; CHECK-NOT @b.1 ; CHECK-NOT: @b.1
@b = internal externally_initialized global {i32, i32} undef, align 4 @b = internal externally_initialized global {i32, i32} undef, align 4
define i32 @foo() { define i32 @foo() {

2
llvm/test/Transforms/InstCombine/convergent.ll
View File

@ -27,7 +27,7 @@ define i32 @no_extern() {
} }
define i32 @indirect_call(i32 ()* %f) { define i32 @indirect_call(i32 ()* %f) {
; CHECK call i32 %f() [[CONVERGENT_ATTR]] ; CHECK: call i32 %f() [[CONVERGENT_ATTR]]
%a = call i32 %f() convergent %a = call i32 %f() convergent
ret i32 %a ret i32 %a
} }

2
llvm/test/Transforms/LoopIdiom/unroll.ll
View File

@ -1,7 +1,7 @@
; RUN: opt -basicaa -loop-idiom < %s -S | FileCheck %s ; RUN: opt -basicaa -loop-idiom < %s -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
; CHECK @.memset_pattern = private unnamed_addr constant [4 x i32] [i32 2, i32 2, i32 2, i32 2], align 16 ; CHECK: @.memset_pattern = private unnamed_addr constant [4 x i32] [i32 2, i32 2, i32 2, i32 2], align 16
target triple = "x86_64-apple-darwin10.0.0" target triple = "x86_64-apple-darwin10.0.0"

4
llvm/test/Transforms/PGOProfile/multiple_hash_profile.ll
View File

@ -27,8 +27,8 @@ entry:
%cmp.i = icmp sgt i32 %i, 2 %cmp.i = icmp sgt i32 %i, 2
%mul.i = select i1 %cmp.i, i32 1, i32 %i %mul.i = select i1 %cmp.i, i32 1, i32 %i
; CHECK: %mul.i = select i1 %cmp.i, i32 1, i32 %i ; CHECK: %mul.i = select i1 %cmp.i, i32 1, i32 %i
; CHECK-SAME !prof ![[BW:[0-9]+]] ; CHECK-SAME: !prof ![[BW:[0-9]+]]
; CHECK ![[BW]] = !{!"branch_weights", i32 12, i32 6} ; CHECK: ![[BW]] = !{!"branch_weights", i32 12, i32 6}
%retval.0.i = mul nsw i32 %mul.i, %i %retval.0.i = mul nsw i32 %mul.i, %i
ret i32 %retval.0.i ret i32 %retval.0.i
} }

2
llvm/test/Transforms/Util/simplify-dbg-declare-load.ll
View File

@ -19,7 +19,7 @@ fail: ; preds = %top
unreachable unreachable
idxend: ; preds = %top idxend: ; preds = %top
; CHECK-NOT call void @llvm.dbg.value(metadata %foo* %cp, ; CHECK-NOT: call void @llvm.dbg.value(metadata %foo* %cp,
%0 = load volatile %foo, %foo* %cp, align 8 %0 = load volatile %foo, %foo* %cp, align 8
; CHECK: call void @llvm.dbg.value(metadata %foo %0, ; CHECK: call void @llvm.dbg.value(metadata %foo %0,
store volatile %foo %0, %foo* undef, align 8 store volatile %foo %0, %foo* undef, align 8