[x86] auto-generate complete checks for tests; NFC
These all used 'CHECK-NOT' which isn't necessary if we have complete checks. llvm-svn: 307024
This commit is contained in:
Sanjay Patel
parent
bd1eb12d31
commit
dab798a25f
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@ -1,38 +1,36 @@
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; RUN: llc < %s -relocation-model=static -march=x86 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -relocation-model=static -mtriple=i686-unknown-unknown | FileCheck %s
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; This should produce two shll instructions, not any lea's.
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target triple = "i686-apple-darwin8"
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@Y = weak global i32 0 ; <i32*> [#uses=1]
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@X = weak global i32 0 ; <i32*> [#uses=2]
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@Y = weak global i32 0
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@X = weak global i32 0
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define void @fn1() {
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; CHECK-LABEL: fn1:
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; CHECK-NOT: ret
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; CHECK-NOT: lea
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; CHECK: shll $3
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; CHECK-NOT: lea
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; CHECK: ret
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%tmp = load i32, i32* @Y ; <i32> [#uses=1]
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%tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1]
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%tmp2 = load i32, i32* @X ; <i32> [#uses=1]
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%tmp3 = or i32 %tmp1, %tmp2 ; <i32> [#uses=1]
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; CHECK: # BB#0:
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; CHECK-NEXT: movl Y, %eax
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; CHECK-NEXT: shll $3, %eax
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; CHECK-NEXT: orl %eax, X
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; CHECK-NEXT: retl
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%tmp = load i32, i32* @Y
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%tmp1 = shl i32 %tmp, 3
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%tmp2 = load i32, i32* @X
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%tmp3 = or i32 %tmp1, %tmp2
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store i32 %tmp3, i32* @X
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ret void
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}
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define i32 @fn2(i32 %X, i32 %Y) {
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; CHECK-LABEL: fn2:
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; CHECK-NOT: ret
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; CHECK-NOT: lea
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; CHECK: shll $3
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; CHECK-NOT: lea
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; CHECK: ret
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%tmp2 = shl i32 %Y, 3 ; <i32> [#uses=1]
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%tmp4 = or i32 %tmp2, %X ; <i32> [#uses=1]
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: shll $3, %eax
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; CHECK-NEXT: orl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: retl
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%tmp2 = shl i32 %Y, 3
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%tmp4 = or i32 %tmp2, %X
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ret i32 %tmp4
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}
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@ -1,12 +1,13 @@
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; RUN: llc < %s -march=x86 -verify-coalescing | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -verify-coalescing | FileCheck %s
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define i32* @test1(i32* %P, i32 %X) {
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; CHECK-LABEL: test1:
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; CHECK-NOT: shrl
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; CHECK-NOT: shll
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; CHECK: ret
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entry:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: andl $-4, %eax
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: retl
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%Y = lshr i32 %X, 2
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%gep.upgrd.1 = zext i32 %Y to i64
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%P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.1
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@ -15,11 +16,11 @@ entry:
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define i32* @test2(i32* %P, i32 %X) {
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; CHECK-LABEL: test2:
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; CHECK: shll $4
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; CHECK-NOT: shll
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; CHECK: ret
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entry:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: shll $4, %eax
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: retl
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%Y = shl i32 %X, 2
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%gep.upgrd.2 = zext i32 %Y to i64
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%P2 = getelementptr i32, i32* %P, i64 %gep.upgrd.2
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@ -28,11 +29,11 @@ entry:
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define i32* @test3(i32* %P, i32 %X) {
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; CHECK-LABEL: test3:
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; CHECK-NOT: shrl
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; CHECK-NOT: shll
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; CHECK: ret
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entry:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: andl $-4, %eax
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; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: retl
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%Y = ashr i32 %X, 2
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%P2 = getelementptr i32, i32* %P, i32 %Y
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ret i32* %P2
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@ -40,25 +41,27 @@ entry:
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define fastcc i32 @test4(i32* %d) {
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; CHECK-LABEL: test4:
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; CHECK-NOT: shrl
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; CHECK: ret
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entry:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl 3(%ecx), %eax
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; CHECK-NEXT: retl
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%tmp4 = load i32, i32* %d
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%tmp512 = lshr i32 %tmp4, 24
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ret i32 %tmp512
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}
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define i64 @test5(i16 %i, i32* %arr) {
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; Ensure that we don't fold away shifts which have multiple uses, as they are
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; just re-introduced for the second use.
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; CHECK-LABEL: test5:
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; CHECK-NOT: shrl
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; CHECK: shrl $11
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; CHECK-NOT: shrl
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; CHECK: ret
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entry:
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define i64 @test5(i16 %i, i32* %arr) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: shrl $11, %eax
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; CHECK-NEXT: xorl %edx, %edx
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; CHECK-NEXT: addl (%ecx,%eax,4), %eax
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; CHECK-NEXT: setb %dl
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; CHECK-NEXT: retl
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%i.zext = zext i16 %i to i32
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%index = lshr i32 %i.zext, 11
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%index.zext = zext i32 %index to i64
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@ -1,4 +1,5 @@
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx2 | FileCheck %s
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; Test that we correctly fold a shuffle that performs a swizzle of another
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; shuffle node according to the rule
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@ -11,81 +12,77 @@
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; Check that we produce a single vector permute / shuffle in all cases.
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define <8 x i32> @swizzle_1(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_1:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [1,3,2,0,4,5,6,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 3, i32 1, i32 2, i32 0, i32 7, i32 5, i32 6, i32 4>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 7, i32 5, i32 6, i32 4>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_1
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; CHECK: vpermd
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; CHECK-NOT: vpermd
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; CHECK: ret
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define <8 x i32> @swizzle_2(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_2:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 6, i32 7, i32 4, i32 5, i32 0, i32 1, i32 2, i32 3>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_2
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; CHECK: vpshufd $78
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; CHECK-NOT: vpermd
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; CHECK-NOT: vpshufd
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; CHECK: ret
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define <8 x i32> @swizzle_3(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_3:
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; CHECK: # BB#0:
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; CHECK-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[2,3,0,1,6,7,4,5]
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_3
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; CHECK: vpshufd $78
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; CHECK-NOT: vpermd
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; CHECK-NOT: vpshufd
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; CHECK: ret
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define <8 x i32> @swizzle_4(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_4:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [3,1,2,0,6,5,4,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 4, i32 7, i32 5, i32 6, i32 3, i32 2, i32 0, i32 1>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 4, i32 7, i32 5, i32 6, i32 3, i32 2, i32 0, i32 1>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_4
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; CHECK: vpermd
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; CHECK-NOT: vpermd
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; CHECK: ret
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define <8 x i32> @swizzle_5(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_5:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [3,0,1,2,7,6,4,5]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 7, i32 4, i32 6, i32 5, i32 0, i32 2, i32 1, i32 3>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 7, i32 4, i32 6, i32 5, i32 0, i32 2, i32 1, i32 3>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_5
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; CHECK: vpermd
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; CHECK-NOT: vpermd
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; CHECK: ret
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define <8 x i32> @swizzle_6(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_6:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [3,1,0,2,4,5,6,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 2, i32 1, i32 3, i32 0, i32 4, i32 7, i32 6, i32 5>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 2, i32 1, i32 3, i32 0, i32 4, i32 7, i32 6, i32 5>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_6
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; CHECK: vpermd
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; CHECK-NOT: vpermd
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; CHECK: ret
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define <8 x i32> @swizzle_7(<8 x i32> %v) {
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; CHECK-LABEL: swizzle_7:
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; CHECK: # BB#0:
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; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [0,2,3,1,4,5,6,7]
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; CHECK-NEXT: vpermd %ymm0, %ymm1, %ymm0
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; CHECK-NEXT: retq
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%1 = shufflevector <8 x i32> %v, <8 x i32> undef, <8 x i32> <i32 0, i32 3, i32 1, i32 2, i32 5, i32 4, i32 6, i32 7>
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%2 = shufflevector <8 x i32> %1, <8 x i32> undef, <8 x i32> <i32 0, i32 3, i32 1, i32 2, i32 5, i32 4, i32 6, i32 7>
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ret <8 x i32> %2
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}
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; CHECK-LABEL: swizzle_7
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; CHECK: vpermd
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; CHECK-NOT: vpermd
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; CHECK: ret
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@ -1,253 +1,255 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+tbm < %s | FileCheck %s
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define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u32:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = lshr i32 %a, 4
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%1 = and i32 %0, 4095
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ret i32 %1
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define i32 @test_x86_tbm_bextri_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u32:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
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; CHECK-NEXT: retq
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%t0 = lshr i32 %a, 4
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%t1 = and i32 %t0, 4095
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ret i32 %t1
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}
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define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind readonly {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = load i32, i32* %a
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%1 = lshr i32 %0, 4
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%2 = and i32 %1, 4095
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ret i32 %2
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define i32 @test_x86_tbm_bextri_u32_m(i32* nocapture %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u32_m:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextr $3076, (%rdi), %eax # imm = 0xC04
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; CHECK-NEXT: retq
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%t0 = load i32, i32* %a
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%t1 = lshr i32 %t0, 4
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%t2 = and i32 %t1, 4095
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ret i32 %t2
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}
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define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u64:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = lshr i64 %a, 4
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%1 = and i64 %0, 4095
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ret i64 %1
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define i64 @test_x86_tbm_bextri_u64(i64 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u64:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextr $3076, %edi, %eax # imm = 0xC04
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; CHECK-NEXT: retq
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%t0 = lshr i64 %a, 4
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%t1 = and i64 %t0, 4095
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ret i64 %t1
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}
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define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind readonly {
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entry:
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; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
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; CHECK-NOT: mov
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; CHECK: bextr $
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%0 = load i64, i64* %a
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%1 = lshr i64 %0, 4
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%2 = and i64 %1, 4095
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ret i64 %2
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define i64 @test_x86_tbm_bextri_u64_m(i64* nocapture %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_bextri_u64_m:
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; CHECK: # BB#0:
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; CHECK-NEXT: bextr $3076, (%rdi), %eax # imm = 0xC04
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; CHECK-NEXT: retq
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%t0 = load i64, i64* %a
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%t1 = lshr i64 %t0, 4
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%t2 = and i64 %t1, 4095
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ret i64 %t2
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}
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define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind readnone {
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entry:
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; CHECK-LABEL: test_x86_tbm_blcfill_u32:
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; CHECK-NOT: mov
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; CHECK: blcfill %
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%0 = add i32 %a, 1
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%1 = and i32 %0, %a
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ret i32 %1
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define i32 @test_x86_tbm_blcfill_u32(i32 %a) nounwind {
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; CHECK-LABEL: test_x86_tbm_blcfill_u32:
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; CHECK: # BB#0:
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; CHECK-NEXT: blcfill %edi, %eax
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; CHECK-NEXT: retq
|
||||
%t0 = add i32 %a, 1
|
||||
%t1 = and i32 %t0, %a
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcfill_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcfill %
|
||||
%0 = add i64 %a, 1
|
||||
%1 = and i64 %0, %a
|
||||
ret i64 %1
|
||||
define i64 @test_x86_tbm_blcfill_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcfill_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcfill %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i64 %a, 1
|
||||
%t1 = and i64 %t0, %a
|
||||
ret i64 %t1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blci %
|
||||
%0 = add i32 1, %a
|
||||
%1 = xor i32 %0, -1
|
||||
%2 = or i32 %1, %a
|
||||
ret i32 %2
|
||||
define i32 @test_x86_tbm_blci_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blci %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i32 1, %a
|
||||
%t1 = xor i32 %t0, -1
|
||||
%t2 = or i32 %t1, %a
|
||||
ret i32 %t2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blci %
|
||||
%0 = add i64 1, %a
|
||||
%1 = xor i64 %0, -1
|
||||
%2 = or i64 %1, %a
|
||||
ret i64 %2
|
||||
define i64 @test_x86_tbm_blci_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blci %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i64 1, %a
|
||||
%t1 = xor i64 %t0, -1
|
||||
%t2 = or i64 %t1, %a
|
||||
ret i64 %t2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u32_b:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blci %
|
||||
%0 = sub i32 -2, %a
|
||||
%1 = or i32 %0, %a
|
||||
ret i32 %1
|
||||
define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u32_b:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blci %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = sub i32 -2, %a
|
||||
%t1 = or i32 %t0, %a
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u64_b:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blci %
|
||||
%0 = sub i64 -2, %a
|
||||
%1 = or i64 %0, %a
|
||||
ret i64 %1
|
||||
define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blci_u64_b:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blci %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = sub i64 -2, %a
|
||||
%t1 = or i64 %t0, %a
|
||||
ret i64 %t1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcic_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcic %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, 1
|
||||
%2 = and i32 %1, %0
|
||||
ret i32 %2
|
||||
define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcic_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcic %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i32 %a, -1
|
||||
%t1 = add i32 %a, 1
|
||||
%t2 = and i32 %t1, %t0
|
||||
ret i32 %t2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcic_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcic %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, 1
|
||||
%2 = and i64 %1, %0
|
||||
ret i64 %2
|
||||
define i64 @test_x86_tbm_blcic_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcic_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcic %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, 1
|
||||
%t2 = and i64 %t1, %t0
|
||||
ret i64 %t2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcmsk_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcmsk %
|
||||
%0 = add i32 %a, 1
|
||||
%1 = xor i32 %0, %a
|
||||
ret i32 %1
|
||||
define i32 @test_x86_tbm_blcmsk_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcmsk_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcmsk %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i32 %a, 1
|
||||
%t1 = xor i32 %t0, %a
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcmsk_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcmsk %
|
||||
%0 = add i64 %a, 1
|
||||
%1 = xor i64 %0, %a
|
||||
ret i64 %1
|
||||
define i64 @test_x86_tbm_blcmsk_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcmsk_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcmsk %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i64 %a, 1
|
||||
%t1 = xor i64 %t0, %a
|
||||
ret i64 %t1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcs_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcs %
|
||||
%0 = add i32 %a, 1
|
||||
%1 = or i32 %0, %a
|
||||
ret i32 %1
|
||||
define i32 @test_x86_tbm_blcs_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcs_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcs %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i32 %a, 1
|
||||
%t1 = or i32 %t0, %a
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blcs_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blcs %
|
||||
%0 = add i64 %a, 1
|
||||
%1 = or i64 %0, %a
|
||||
ret i64 %1
|
||||
define i64 @test_x86_tbm_blcs_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blcs_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blcs %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i64 %a, 1
|
||||
%t1 = or i64 %t0, %a
|
||||
ret i64 %t1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsfill_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsfill %
|
||||
%0 = add i32 %a, -1
|
||||
%1 = or i32 %0, %a
|
||||
ret i32 %1
|
||||
define i32 @test_x86_tbm_blsfill_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blsfill_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blsfill %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i32 %a, -1
|
||||
%t1 = or i32 %t0, %a
|
||||
ret i32 %t1
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsfill_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsfill %
|
||||
%0 = add i64 %a, -1
|
||||
%1 = or i64 %0, %a
|
||||
ret i64 %1
|
||||
define i64 @test_x86_tbm_blsfill_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blsfill_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blsfill %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = add i64 %a, -1
|
||||
%t1 = or i64 %t0, %a
|
||||
ret i64 %t1
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsic %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, -1
|
||||
%2 = or i32 %0, %1
|
||||
ret i32 %2
|
||||
define i32 @test_x86_tbm_blsic_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blsic %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i32 %a, -1
|
||||
%t1 = add i32 %a, -1
|
||||
%t2 = or i32 %t0, %t1
|
||||
ret i32 %t2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: blsic %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, -1
|
||||
%2 = or i64 %0, %1
|
||||
ret i64 %2
|
||||
define i64 @test_x86_tbm_blsic_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_blsic_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: blsic %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, -1
|
||||
%t2 = or i64 %t0, %t1
|
||||
ret i64 %t2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: t1mskc %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, 1
|
||||
%2 = or i32 %0, %1
|
||||
ret i32 %2
|
||||
define i32 @test_x86_tbm_t1mskc_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: t1mskc %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i32 %a, -1
|
||||
%t1 = add i32 %a, 1
|
||||
%t2 = or i32 %t0, %t1
|
||||
ret i32 %t2
|
||||
}
|
||||
|
||||
define i64 @Ttest_x86_tbm_t1mskc_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_t1mskc_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: t1mskc %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, 1
|
||||
%2 = or i64 %0, %1
|
||||
ret i64 %2
|
||||
define i64 @Ttest_x86_tbm_t1mskc_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: Ttest_x86_tbm_t1mskc_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: t1mskc %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, 1
|
||||
%t2 = or i64 %t0, %t1
|
||||
ret i64 %t2
|
||||
}
|
||||
|
||||
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: tzmsk %
|
||||
%0 = xor i32 %a, -1
|
||||
%1 = add i32 %a, -1
|
||||
%2 = and i32 %0, %1
|
||||
ret i32 %2
|
||||
define i32 @test_x86_tbm_tzmsk_u32(i32 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u32:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: tzmsk %edi, %eax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i32 %a, -1
|
||||
%t1 = add i32 %a, -1
|
||||
%t2 = and i32 %t0, %t1
|
||||
ret i32 %t2
|
||||
}
|
||||
|
||||
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:
|
||||
; CHECK-NOT: mov
|
||||
; CHECK: tzmsk %
|
||||
%0 = xor i64 %a, -1
|
||||
%1 = add i64 %a, -1
|
||||
%2 = and i64 %0, %1
|
||||
ret i64 %2
|
||||
define i64 @test_x86_tbm_tzmsk_u64(i64 %a) nounwind {
|
||||
; CHECK-LABEL: test_x86_tbm_tzmsk_u64:
|
||||
; CHECK: # BB#0:
|
||||
; CHECK-NEXT: tzmsk %rdi, %rax
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = xor i64 %a, -1
|
||||
%t1 = add i64 %a, -1
|
||||
%t2 = and i64 %t0, %t1
|
||||
ret i64 %t2
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue