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Remove a processFixupValue hack. 

The intention of processFixupValue is not to redefine the semantics of
MCExpr. It is odd enough that a expression lowers to a PCRel MCExpr or
not depending on what it looks like. At least it is a local hack now.

I left a fix for anyone trying to figure out what producers should be
producing a different expression.

llvm-svn: 306200
This commit is contained in:
Rafael Espindola 2017-06-24 05:12:29 +00:00
parent b05f4a7b25
commit daaee7151b
2 changed files with 32 additions and 35 deletions
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31
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@ -30,12 +30,6 @@ public:
unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; };
void processFixupValue(const MCAssembler &Asm,
const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF,
const MCValue &Target, uint64_t &Value,
bool &IsResolved) override;
void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target, MutableArrayRef<char> Data,
uint64_t Value, bool IsPCRel) const override;
@ -103,31 +97,6 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
}
}
void AMDGPUAsmBackend::processFixupValue(const MCAssembler &Asm,
const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF,
const MCValue &Target, uint64_t &Value,
bool &IsResolved) {
MCValue Res;
// When we have complex expressions like: BB0_1 + (BB0_2 - 4), which are
// used for long branches, this function will be called with
// IsResolved = false and Value set to some pre-computed value. In
// the example above, the value would be:
// (BB0_1 + (BB0_2 - 4)) - CurrentOffsetFromStartOfFunction.
// This is not what we want. We just want the expression computation
// only. The reason the MC layer subtracts the current offset from the
// expression is because the fixup is of kind FK_PCRel_4.
// For these scenarios, evaluateAsValue gives us the computation that we
// want.
if (!IsResolved && Fixup.getValue()->evaluateAsValue(Res, Layout) &&
Res.isAbsolute()) {
Value = Res.getConstant();
IsResolved = true;
}
}
void AMDGPUAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
const MCValue &Target,
MutableArrayRef<char> Data, uint64_t Value,

36
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
View File

@ -363,6 +363,25 @@ SIMCCodeEmitter::getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo,
return RegEnc;
}
static bool needsPCRel(const MCExpr *Expr) {
switch (Expr->getKind()) {
case MCExpr::SymbolRef:
return true;
case MCExpr::Binary: {
auto *BE = cast<MCBinaryExpr>(Expr);
if (BE->getOpcode() == MCBinaryExpr::Sub)
return false;
return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
}
case MCExpr::Unary:
return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
case MCExpr::Target:
case MCExpr::Constant:
return false;
}
llvm_unreachable("invalid kind");
}
uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
const MCOperand &MO,
SmallVectorImpl<MCFixup> &Fixups,
@ -371,12 +390,21 @@ uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
return MRI.getEncodingValue(MO.getReg());
if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
const auto *Expr = dyn_cast<MCSymbolRefExpr>(MO.getExpr());
// FIXME: If this is expression is PCRel or not should not depend on what
// the expression looks like. Given that this is just a general expression,
// it should probably be FK_Data_4 and whatever is producing
//
// s_add_u32 s2, s2, (extern_const_addrspace+16
//
// And expecting a PCRel should instead produce
//
// .Ltmp1:
// s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
MCFixupKind Kind;
if (Expr && Expr->getSymbol().isExternal())
Kind = FK_Data_4;
else
if (needsPCRel(MO.getExpr()))
Kind = FK_PCRel_4;
else
Kind = FK_Data_4;
Fixups.push_back(MCFixup::create(4, MO.getExpr(), Kind, MI.getLoc()));
}