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[AMDGPU] Silence gcc 7 warnings 

Differential Revision: https://reviews.llvm.org/D59330

llvm-svn: 356100
This commit is contained in:
Stanislav Mekhanoshin 2019-03-13 21:15:52 +00:00
parent 55881d5def
commit da644c025d
5 changed files with 9 additions and 38 deletions
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30
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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@ -199,7 +199,6 @@ private:
bool SelectVOP3PMadMixMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
SDValue getHi16Elt(SDValue In) const;
bool SelectHi16Elt(SDValue In, SDValue &Src) const;
void SelectADD_SUB_I64(SDNode *N);
void SelectUADDO_USUBO(SDNode *N);
@ -2215,35 +2214,6 @@ SDValue AMDGPUDAGToDAGISel::getHi16Elt(SDValue In) const {
return SDValue();
}
// TODO: Can we identify things like v_mad_mixhi_f16?
bool AMDGPUDAGToDAGISel::SelectHi16Elt(SDValue In, SDValue &Src) const {
if (In.isUndef()) {
Src = In;
return true;
}
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(In)) {
SDLoc SL(In);
SDValue K = CurDAG->getTargetConstant(C->getZExtValue() << 16, SL, MVT::i32);
MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
SL, MVT::i32, K);
Src = SDValue(MovK, 0);
return true;
}
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(In)) {
SDLoc SL(In);
SDValue K = CurDAG->getTargetConstant(
C->getValueAPF().bitcastToAPInt().getZExtValue() << 16, SL, MVT::i32);
MachineSDNode *MovK = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
SL, MVT::i32, K);
Src = SDValue(MovK, 0);
return true;
}
return isExtractHiElt(In, Src);
}
bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
return false;

6
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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@ -102,14 +102,14 @@ public:
int64_t getFPModifiersOperand() const {
int64_t Operand = 0;
Operand |= Abs ? SISrcMods::ABS : 0;
Operand |= Neg ? SISrcMods::NEG : 0;
Operand |= Abs ? SISrcMods::ABS : 0u;
Operand |= Neg ? SISrcMods::NEG : 0u;
return Operand;
}
int64_t getIntModifiersOperand() const {
int64_t Operand = 0;
Operand |= Sext ? SISrcMods::SEXT : 0;
Operand |= Sext ? SISrcMods::SEXT : 0u;
return Operand;
}

4
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View File

@ -823,9 +823,9 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
using namespace AMDGPU::EncValues;
if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) {
// XXX: static_cast<int> is needed to avoid stupid warning:
// XXX: cast to int is needed to avoid stupid warning:
// compare with unsigned is always true
if (SDWA9EncValues::SRC_VGPR_MIN <= Val &&
if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
Val <= SDWA9EncValues::SRC_VGPR_MAX) {
return createRegOperand(getVgprClassId(Width),
Val - SDWA9EncValues::SRC_VGPR_MIN);

3
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
View File

@ -925,7 +925,8 @@ const MachineOperand *SIFoldOperands::isClamp(const MachineInstr &MI) const {
// Having a 0 op_sel_hi would require swizzling the output in the source
// instruction, which we can't do.
unsigned UnsetMods = (Op == AMDGPU::V_PK_MAX_F16) ? SISrcMods::OP_SEL_1 : 0;
unsigned UnsetMods = (Op == AMDGPU::V_PK_MAX_F16) ? SISrcMods::OP_SEL_1
: 0u;
if (Src0Mods != UnsetMods && Src1Mods != UnsetMods)
return nullptr;
return Src0;

4
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
View File

@ -347,8 +347,8 @@ uint64_t SDWASrcOperand::getSrcMods(const SIInstrInfo *TII,
if (Abs || Neg) {
assert(!Sext &&
"Float and integer src modifiers can't be set simulteniously");
Mods |= Abs ? SISrcMods::ABS : 0;
Mods ^= Neg ? SISrcMods::NEG : 0;
Mods |= Abs ? SISrcMods::ABS : 0u;
Mods ^= Neg ? SISrcMods::NEG : 0u;
} else if (Sext) {
Mods |= SISrcMods::SEXT;
}